Showing papers on "Breakdown voltage published in 1987"

Modern power devices

Abstract: Carrier Transport Physics Breakdown Voltage Power Junction Field-Effect Transistors Power Field-Controlled Diodes Power Metal-Oxide-Semiconductor Field Effect Transistors Power MOS-Bipolar Devices New Rectifier Concepts Synopsis References Index

The impact of gate-induced drain leakage current on MOSFET scaling

Abstract: Significant gate-induced drain leakage current can be detected in thin gate oxide MOSFETs at drain voltages much lower than the junction breakdown voltage. This current is found to be due to the band-to-band tunneling occurring in the deep-depletion layer in the gate-to-drain overlap region. In order to limit the leakage current to 0.1pA/µm, the oxide field in the gate-to-drain overlap region must be limited to 1.9MV/cm. This may set another constraint for the power supply voltage and/or oxide thickness in VLSI MOSFET scaling Device design considerations for minimizing the gate-induced drain leakage current are discussed.

A true single-transistor oxide-nitride-oxide EEPROM device

Abstract: A novel single-transistor EEPROM device using single-polysilicon technology is described. This memory is programmed by channel hot-electron injection and the charges are stored in the oxide-nitride-oxide (ONO) gate dielectric. Erasing is accomplished in milliseconds by applying a positive voltage to the drain plus an optional negative voltage to the gate causing electron tunneling and/or hot-hole injection due to the deep-depletion-mode drain breakdown. Since the injection and storage of electrons and holes are confined to a short region near the drain, the part of the channel near the source maintains the original positive threshold voltage even after repeated erase operation. Therefore a select transistor, separate or integral, is not needed. Because oxide layers with a thickness larger than 60 A are used, this device has much better data retention characteristics than conventional MNOS memory cells. This device has been successfully tested for WRITE/ERASE endurance to 10000 cycles.

Subbreakdown drain leakage current in MOSFET

Abstract: Significant drain leakage current can be detected at drain voltages much lower than the breakdown voltage. This subbreakdown leakage can dominate the drain leakage current at zero V G in thin-oxide MOSFET's. The mechanism is shown to be band-to-band tunneling in Si in the drain/gate overlap region. In order to limit the leakage current to 0.1 pA/µm, the oxide field in the gate-to-drain overlap region must be limited to 2.2 MV/cm. This may set another constraint for oxide thickness or power supply voltage.

Breakdown properties of quenched random systems: The random-fuse network.

Abstract: An analysis of a prototypical percolation model (the fuse network) for breakdown in quenched random systems is given. The breakdown voltage and the topology of the eventual breakdown path are studied analytically and numerically. New scaling concepts, based on the most critical defect in the network, combined with standard percolation scaling ideas, lead to a complete picture of the strength of the network. The mean breakdown strength and the distribution of breakdown strengths are derived in the different concentration regimes. The breakdown path is described by new order parameters on approach to ${p}_{c}$. One, the number of bonds broken in the breakdown process, is studied in detail. Many models and physical systems should show an analogous behavior and simplified models for two of these problems, brittle fracture and dielectric breakdown in solids, are discussed.

An ultra-low on-resistance power MOSFET fabricated by using a fully self-aligned process

Abstract: An ultra-low on-resistance power MOSFET fabricated by use of a fully self-aligned process is demonstrated. The feature of the new process is that most of the processing steps, such as channel formation, gate definition, and contact-hole opening, are carried out through a single masking step. This permits a remarkable increase in packing density, and thereby conducts the reduction of the channel resistance. A gate width per unit area of 50 cm /mm2has been implemented by using the new process with a 4-µm-pitch layout rule. This value is at least four times larger than that of the conventional VDMOSFET. The experimentally fabricated device, which possesses a total gate width of 480 cm in a 3.8 mm × 4.0 mm chip, exhibited an on-resistance of 9 mΩ and a breakdown voltage of 30 V. The resulting on-resistance area product of 137 mΩ .mm2is the smallest value ever reported.

Self-aligned UMOSFET's with a specific on-resistance of 1 mΩ.cm 2

Abstract: This paper describes an improved UMOSFET with an ultralow specific on-resistance. This device utilizes a self-aligned process that permits closely spaced vertical trench gates with a unit cell of 6 µm. This allows for a remarkable increase of channel density and, therefore, reduces the on-resistance per unit area significantly. Experimental devices have been fabricated, and a specific on-resistance of 1.0 mΩ . cm2with a breakdown voltage of 30 V has been achieved. This specific on-resistance is the lowest value ever reported for FET's.

Monolithic integration of InGaAsP/InP distributed feedback laser and electroabsorption modulator by vapor phase epitaxy

Abstract: Monolithic integration of a 1.55-μm InGaAsP/InP distributed feedback (DFB) laser and an electroabsorption (EA) modulator was studied. The difference between the lasing photon energy and the bandgap energy of the modulator waveguide was designed to be 30-40 meV, taking into account the linewidth-enhancement factor and the zero-bias absorption loss. The integrated devices were grown by three-step vapor phase epitaxy (VPE). The CW threshold current at 20°C of the DFB laser part with a buried heterostructure was 30-60 mA and the breakdown voltage of the modulator part with a strip-loaded stripe geometry was 20-40 V, and these values indicated satisfactory crystal quality in the VPE epitaxial layers. The operating voltage of the modulator to give on:off ratios of 10:1 and 100:1 was 1.5- 4 V and 2.5-6.5 V, respectively, depending on the length in the range 200-500 \mu m. A 3-dB bandwidth of about 2.5 GHz and a linewidth-enhancement factor of about 1.6 were obtained for the integrated modulator.

Vertical double diffused metal oxide semiconductor (VDMOS) device including high voltage junction exhibiting increased safe operating area

Abstract: A power field effect device has a high voltage blocking junction which intersects the device surface under the gate electrode. That intersection is a closed plane geometric figure whose center is within the body region of the device rather than in the more heavily doped base region of the device. The figure preferably is everywhere convex and has a maximum width of substantially less than the depletion width, at breakdown, of a corresponding parallel plane junction. The device breakdown voltage is higher than the breakdown voltage of a corresponding junction having a cylindrical edge with a straight axis. In a preferred embodiment, the high voltage blocking junction has a plurality of such intersections with the device surface, each situated beneath a segment of the gate electrode. In a bipolar embodiment, the gate electrode may be omitted.

Surface potential effect on gate—Drain avalanche breakdown in GaAs MESFET's

Abstract: The surface potential effect on gate-drain avalanche breakdown in GaAs MESFET's is investigated with a two-dimensional device simulator. It is shown that the surface potential effect changes the potential distribution in GaAs MESFET's drastically and therefore plays an important role in determining drain breakdown voltage. In addition, two device structures producing high breakdown voltages, an offset gate structure and a recessed gate structure, are analyzed.

Insulated gate bipolar transistor (IGBT) with a trench gate structure

Abstract: This paper describes an improved IGBT with a trench gate structure, which demonstrates a low forward voltage drop of 1.4 volts at a forward conduction current density of 200A/cm2. This device structure was fabricated using a self-aligned process that permits closely spaced vertical trench gates with a unit cell of 8 µm. This allows for a remarkable increase of channel density and elimination of the parasitic JFET effect thus reducing the forward voltage drop significantly. A static latching current density of 2700A/cm2has been achieved in the UMOS IGBT. Two-dimensional computer simulations of the UMOS IGBT has been performed to identify the optimal cell design. This optimal design is predicted to increase the SOA current density by a factor of 4.2 over the state-of-the-art DMOS IGBT at the same forward voltage drop.

Source drain doping technique

Abstract: A method of forming complementary metal oxide semiconductor field-effect transistors (CMOSFET) is described wherein the source and drain regions are disposed by ion implantation in a manner substantially perpendicular to the substrate surface in two steps, such that the concentration of impurities increases with lateral distance away from the gate electrode member to suppress the hot e injection, to prevent channeling effects, to increase punch through voltage and to increase gate-aided breakdown voltage.

Hydrogenation of GaAs on Si: Effects on diode reverse leakage current

Abstract: Plasma hydrogenation for 3 h at 250 °C of GaAs layers grown directly on Si substrates by metalorganic chemical vapor deposition, followed by a 5‐min, 400 °C anneal to restore the passivated shallow donor electrical activity, increases the reverse breakdown voltage of Schottky diode structures from 2.5 to 6.5 V. This improvement appears to be a result of the passivation by atomic hydrogen of defects such as threading dislocations caused by the large (4%) lattice mismatch between GaAs and Si. A reduced Schottky barrier height is exhibited by hydrogenated samples, consistent with As depletion of the surface occurring during the long duration plasma processing.

Thermal-buble initiated breakdown characteristics of liquid helium and nitrogen at atmospheric pressure

Abstract: Experiments show that electric field promotes to form a vapor locking in a gap with a hot spot and in turn the formation of locked vapor produces the serious reduction of breakdown voltage. Especially it is argued that the dielectric strengh of liquid helium under serious hot spot conditions decreases below that for saturated gas.

Telephone and data overvoltage protection apparatus

Abstract: Overvoltage protection circuits are provided for coupling a subscriber's station to first and second conductors connected to a telephone system or other similar communications source. The overvoltage protection circuits include first circuitry connected between the first and second conductors for conducting current at a first breakdown voltage and for blocking current below the first breakdown voltage; second circuitry for conducting current at a second breakdown voltage and for blocking current below the second breakdown voltage; and circuitry connected in series between the first and second circuitry for filtering voltage signals on the first and second conductors responsive to the second circuitry conducting current. The overvoltage protection circuits are effective for suppressing noise and transient voltage signals occurring above the data signal and do not require a transient voltage signal to exceed the ring signal for operation.

Multiple-zone single-mask junction termination extension—A high-yield near-ideal breakdown voltage technology

Abstract: The junction termination extension (JTE) technique of Temple is investigated in detail by computer simulation and experimentally. A multiple-zone JTE can be fabricated with a well-controlled single ion-implantation through a single mask with laterally variable transparencies. Analog I-V trace records of over 40 000 samples were obtained for analysis. By grouping 49 JTE designs onto region of the wafer, the effects of the JTE variations and the material variations are separated. The JTE performance agrees well with the computer results. The multiple-zone JTE of sufficient extension size achieves an essentially ideal breakdown voltage unaffected by even a factor of two in ion-implant dose variations. The JTE performs well on both n- and p-type wafers. A best design has been applied to several lots of power devices, and a yield of 99.5 percent having breakdown-voltage values within 10 percent of the ideal has been obtained. The single-mask technique assures the producibility of this 100-percent guard JTE technology, which consumes only 30 percent of the extension area needed by field rings that, at best, produced about 70 percent of the ideal breakdown voltage.

Parasitic bipolar effects in submicrometer GaAs MESFET's

Abstract: We report the observation for the first time of parasitic bipolar action in GaAs MESFET's. It manifests itself in the form of increased transconductance at higher drain voltage, abrupt change in output conductance (kink effect) around 4-V drain-source voltage, and a gate-voltage-dependent substrate current. These effects are explained by electron-hole pair generation in the high-field region at the drain. The holes generated are injected into the substrate where they form the base region of a parasitic lateral bipolar transistor. The effect also explains a new breakdown mechanism for short-channel enhancement-mode MESFET's.

High voltage capacitor

Abstract: A high voltage capacitor used for a low-pass filter circuit or the like in a magnetron oscillator circuit of an electronic cooking range includes in combination, a capacitor unit, a ground terminal into which the unit is inserted, two perforating conductors inserted through two through-bores extending in the capacitor unit, insulating casings encircling the capacitor unit on both sides of the ground terminal, insulating resin disposed in both of the insulating casings and surrounding the capacitor unit, an electrode at the outer periphery of the capacitor unit, and electrodes at the inner periphery of each through-bore which surround and are conductively coupled to each perforating conductor. When compared to a conventional high voltage capacitor, the present invention has a reduced number of components, is simple in construction, and is not subject to a lowering of the breakdown voltage durability caused by a heat cycle or the like.

Fabrication of a new type of field-effect transistor using neutralisation of shallow donors by atomic hydrogen in n-GaAs (Si)

Abstract: We describe a new process for the fabrication of GaAs field-effect transistors. This process is based on the neutralisation of shallow donors by atomic hydrogen diffused into a highly silicon-doped epilayer. This original process should be able to produce field-effect transistors with low access resistances. Better linearity and high breakdown voltage are expected owing to the active impurity gradient present in the hydrogenated layer. The first HFETs (hydrogenated FETs) show very encouraging characteristics. For a gate length of 1.2 ?m their typical transconductance is 330 mS/mm and the cutoff frequency is larger than 15 GHz.

Turn-Off Failure of Power MOSFET's

Abstract: Experimental results of the failure of power MOSFET's during inductive turn-off are discussed. The electrical characteristics of these devices during failure are shown to be identical to those of a bipolar transistor undergoing second breakdown. Other comparisons of the power MOSFET failure and bipolar second breakdown are made. A nondestructive measurement system is used that allows repeated measurements of the failure characteristics as a function of various parameters to be made on a single device. It is shown that commercially available power MOSFET's do not fail as a result of dV/dt currents. Drain voltage slew rates up to 22 V/ns were studied. Other measurements show that the drain voltage at which failure occurs increases with temperature, the critical current above which failure occurs decreases with temperature, and the magnitude of the load inductance has no effect on the failure. The results of this study are consistent with the theory that activation of the parasitic bipolar transistor initiates the power MOSFET failure during turn-off.

Opto-electrical power transmission and control system.

Abstract: A laser diode light source (21) is arranged to emit light of a desired intensity (I1), which is transmitted via an optical conductor (22) Light exiting the fiber has an intensity (I2), and falls incident on the receiver surface of a photodiode (23) Such transmitted light provides both the power and control for operating a load (24) The load has a maximum impedance such that the maximum load input voltage required to produce the maximum desired load current does not exceed the forward conductive breakdown voltage of the photodiode

Anodizable strain layer for SOI semiconductor structures

Abstract: A silicon on insulator semiconductor structure employs a strain layer fabricated of an electrically inactive material. The strain layer comprises silicon with a germanium additive to produce a sublayer exhibiting a low breakdown voltage and thus effective for selective anodization.

Characterization of Linear and Nonlinear Properties of GaAs MESFET's for Broad-Band Control Applications

Abstract: GaAs MESFET's designed for control applications have improved switching performance compared to FET's designed for low-noise or high-power amplifiers. A broad-band switching cutoff frequency figure of merit close to 500 GHz has been achieved with both epitaxial and ion-implanted devices having n/sup +/ surface layers and/or channel dopings above 2.0 X 10/sup 17/ cm/sup -3/. Power handling nnder CW conditions is limited in the nonconducting state (FET dc biased into pinchoff) by the difference between the gate breakdown voltage and the pinchoff voltage, while conducting-state power handling is limited by the open-channel current-handling capability. For optimum switching frequency figure of merit, individual gate finger widths greater than those used in amplifier devices for the same maximum frequency of operation are necessary. The large (~5 k Omega) resistor in series with the gate has important ramifications in optimizing the power-handling capability for broad-band applications.

Dielectric breakdown in the presence of random conductors

Abstract: The potential distribution in a random conductor-insulator mixture is obtained here by numerically solving Laplace's equation on a lattice with arbitrary potential boundaries. A new algorithm is introduced for estimating the minimum insulation gap. The average breakdown voltage and the minimum gap for such lattices are estimated for different concentrations of conductors below percolation threshold. Detailed computer-simulation studies in two dimensions indicate that both the average breakdown voltage and the minimum gap variations near the percolation threshold are characterized by the same exponent, equal to the percolation correlation-length exponent.

Low Power Arcjet Thruster Pulse Ignition

Abstract: An investigation of the pulse ignition characteristics of a 1 kW class arcjet using an inductive energy storage pulse generator with a pulse width modulated power converter identified several thruster and pulse generator parameters that influence breakdown voltage including pulse generator rate of voltage rise. This work was conducted with an arcjet tested on hydrogen-nitrogen gas mixtures to simulate fully decomposed hydrazine. Over all ranges of thruster and pulser parameters investigated, the mean breakdown voltages varied from 1.4 to 2.7 kV. Ignition tests at elevated thruster temperatures under certain conditions revealed occasional breakdowns to thruster voltages higher than the power converter output voltage. These post breakdown discharges sometimes failed to transition to the lower voltage arc discharge mode and the thruster would not ignite. Under the same conditions, a transition to the arc mode would occur for a subsequent pulse and the thruster would ignite. An automated 11 600 cycle starting and transition to steady state test demonstrated ignition on the first pulse and required application of a second pulse only two times to initiate breakdown.

Low Temperature Silicon Epitaxy Using Si2 H 6

Abstract: Low temperature epitaxy using at atmospheric pressure was studied for minimizing autodoping from highly doped silicon substrate. The epitaxial growth temperature can be reduced to 800°C with good crystalline quality, i.e., defect density <1/cm2. The thickness of transition layer from highly doped substrate to epilayer was also reduced to below 0.3 μm. A bipolar transistor fabricated in the epilayers grown with this technology exhibited base‐collector breakdown voltage of higher than 25V when the epilayer of about 1 μm thick was used.

Modeling of substrate current in p-MOSFET's

Abstract: It is shown that the substrate current characterization method and modeling approach used for n-MOSFET's is also applicable to p-MOSFET's The impact ionization rate extracted for holes is found to be 8 × 106exp (-37 × 106/E), where E is the electric field Based on our measurement and modeling result, roughly twice the channel electric field is required for p-MOSFET's to generate the same amount of substrate current as n-MOSFET's The hot-carrier-induced breakdown voltage is therefore also about two times larger

Impulse Breakdown Characteristics of Coated Electrodes in SF 6 Gas

Abstract: The authors investigated the impulse breakdown characteristics of coated high-voltage electrodes in SF6 gas with a varying nonuniform factor, electrode area, and coating material. From the viewpoint of the relation between breakdown stress and the stressed electrode area, it was clarified that with coated electrodes, breakdown voltage remains, with an increasing electrode area, nearly at the theoretically estimated level for SF6 gas breakdown without showing any decrease due to the area effect (in contrast to bare electrodes). Moreover, it was also recognized that repeated breakdown characteristics of coated electrodes differed depending on the coating materials.