Showing papers on "Breakdown voltage published in 1988"

Semiconductor devices exhibiting minimum on-resistance

Abstract: An improved conductivity vertical channel semiconductor device includes an insulated gate electrode disposed adjacent a substantial portion of the voltage supporting region. In response to an appropriate bias, the control electrode couples to the electric field originating on charges within the voltage supporting region to reorient the electric field associated with those charges toward the gate electrode and transverse to the direction of current flow through the device. Improved control of the electric field within the voltage supporting region allows the doping concentration, and hence the conductivity of the channel, to be improved without a concomitant decrease in breakdown voltage. Accordingly, the channel width and cell repeat distance of the improved device can be reduced, allowing for an improved current density to be established throughout an overall device cell structure. The charge control region of the voltage supporting layer exhibits an aspect ratio of 0.5.

Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry

Abstract: Power MOSFET apparatus, and method for its production, that suppresses voltage breakdown near the gate, using a polygon-shaped trench in which the gate is positioned, using a shaped deep body junction that partly lies below the trench bottom, and using special procedures for growth of gate oxide at various trench corners.

Inhomogeneous field breakdown in GIS-the prediction of breakdown probabilities and voltages. I. Overview of a theory for inhomogeneous field breakdown in SF/sub 6/

Abstract: Inhomogeneous field breakdown in SF/sub 6/ has been investigated, and a theory has been developed which predicts the breakdown voltage for fast-rising (rectangular) waveforms applied to arbitrary electrode geometries and gas pressures. This theory facilitates the analytical design aspects of many GIS components where previously, engineering judgement and development testing were necessary. It is suggested that extensions of the theory, will permit breakdown voltage prediction for an arbitrary surge waveform, which will facilitate the assessment of test waveform efficacy and the development of a more reliable field, factory, and type tests. >

Theory of dielectric breakdown in metal-loaded dielectrics

Abstract: We have examined a very simple model of dielectric breakdown in random mixtures of metal and dielectric1,2,3 We expect this analysis to be relevant for an class of materials which are composed of a random mixture of metallic particles embedded in a dielectric matrix An example is solid fuel rocket propellant4 which is a mixture of microscopic aluminum particles (the fuel) in a dielectric matrix composed of oxidizer and rubber binder The model we analyze is a percolation model in which the bonds of a d-dimensional lattice with lattice spacing a are occupied by conductors with probability p and by capacitors with probability 1-p The probability p is chosen to be less than the percolation threshold pc so that no conducting path traverses the entire system The breakdown process is modeled by assuming that the capacitors can withstand a maximum voltage drop of 1 volt The entire lattice has a size of L lattice spacings A macroscopic voltage is applied across the lattice This voltage is raised until the voltage drop across one of the capacitors exceeds 1 volt This macroscopic voltage is called V1 the initial breakdown voltage The capacitor which fails is replaced by a conducting element The process of failing one of the capacitors is repeated until a conducting path is formed across the sample The maximum value of the applied voltage during this procedure is called the complete breakdown voltage and is denoted Vb

Avalanche-induced drain-source breakdown in silicon-on-insulator n-MOSFETs

Abstract: A proposed breakdown model includes the effects of floating substrate and finite silicon thickness. The calculated I-V characteristics in the breakdown region agree well with the experimental results. The results show that (1) the drain-source breakdown voltage of silicon-on-insulator (SOI) n-MOSFETs increases with increasing channel length, increasing positive substrate voltage, and decreasing silicon film thickness; and (2) SOI n-MOSFETs have higher breakdown voltage than their bulk-silicon counterparts at large gate bias, but lower breakdown voltage at small gate bias. >

Millimeter-wave diode-grid frequency doubler

Abstract: Monolithic diode grid were fabricated on 2-cm/sup 2/ gallium-arsenide wafers in a proof-of-principle test of a quasi-optical varactor millimeter-wave frequency multiplier array concept. An equivalent circuit model based on a transmission-line analysis of plane wave illumination was applied to predict the array performance. The doubler experiments were performed under far-field illumination conditions. A second-harmonic conversion efficiency of 9.5% and output powers of 0.5 W were achieved at 66 GHz when the diode grid was pumped with a pulsed source at 33 GHz. This grid had 760 Schottky-barrier varactor diodes. The average series resistance was 27 Omega , the minimum capacitance was 18 fF at a reverse breakdown voltage of -3 V. The measurements indicate that the diode grid is a feasible device for generating watt-level powers at millimeter frequencies and that substantial improvement is possible by improving the diode breakdown voltage. >

Passivation of GaAs FET's with PECVD silicon nitride films of different stress states

Abstract: The passivation of GaAs MESFETs with plasma-enhanced chemical-vapor-deposited (PECVD) silicon nitride films of both compressive and tensile stress is reported. Elastic stresses included in GaAs following nitride passivation can produce piezoelectric charge density, which results in a shift of MESFET characteristics. The shift of MESFET parameters due to passivation was found to be dependent on gate orientation. The experiments show that nitride of tensile stress is preferable for MESFETS with (011-bar) oriented gates. The shifts in V/sub TH/,I/sub DSS/, and G/sub M/ of the devices before and after nitride passivation are less than 5% if the nitride of appropriate stress states are used for passivation. The breakdown voltage of the MESFETs after nitride deposition was also studied. It is found that the process with higher hydrogen incorporation tends to reduce the surface oxide and increase the breakdown voltage after nitride deposition. In addition, the passivation of double-channel HEMTs is reported for the first time. >

Dielectric breakdown of polymer films containing metal clusters

Abstract: Thin films of gold‐containing plasma‐polymerized tetrafluoroethylene were prepared in an rf glow discharge. The films thus obtained showed a wide range of conductivities from insulating ( ρ>1016 Ω cm) to metallic ( ρ∼3×10−6 Ω cm), depending on plasma conditions during synthesis. The synthesis of the polymer is described in detail since it presents several new aspects. The structure and composition of the films were investigated by x‐ray photoelectron spectroscopy and transmission electron microscopy. Studies of current‐voltage characteristics in the dielectric regime, i.e., below electrical percolation, show that the conduction is volume limited (Poole–Frenkel effect) in non‐gold‐containing films, and characterized by a bistable switching behavior for gold‐rich films. Dielectric breakdown measurements were realized on self‐healing metal‐insulator‐metal structures. The Weibull analysis of breakdown voltages and a statistical treatment of times to breakdown under constant stress give, respectively, the nomi...

A model for silicon‐oxide breakdown under high field and current stress

Abstract: A recently developed self‐consistent model for gate‐oxide degradation due to charge injection, described in a companion paper, is expanded to include electrical ‘‘wear out’’ breakdown. In the present work, gate‐oxide breakdown is defined to occur when the density of generated neutral trapping sites reaches a critical threshold value at the anode. Breakdown experimental results obtained under constant tunneling current are treated and simulated. The new model deals successfully with oxide breakdown dependence on: injection history, gate‐oxide thickness, charge‐injection current density, injection polarity reversal, gate electrode material, and oxide anneal temperatures.

Drain avalanche breakdown in gallium arsenide MESFET's

Abstract: Avalanche breakdown in GaAs MESFET's simulated by two-dimensional (2-D) numerical calculation with a two-carrier model. The simulation involves electron-hole pair generation due to impact ionization and employs a simplified model of the surface depletion layer of GaAs. Gate-bias-dependent drain breakdown voltage is demonstrated. The effect of the surface depletion layer, drain-to-gate spacing and n/sup +/ layer under the drain contact upon the breakdown voltage is demonstrated. It is clarified that the surface depletion layer has a pronounced effect on the gate-bias dependence of the breakdown voltage. The breakdown mechanism is explained in terms of conductivity modulation in the semi-insulting substrate. >

Thermal-bubble initiated breakdown characteristics of liquid helium and nitrogen at atmospheric pressure

Abstract: Results of an experimental study on the DC breakdown characteristics of liquid helium and nitrogen in the presence of thermally created bubbles are presented. These results show that the bubble shape is affected significantly by the application of an electric field, and that the breakdown voltage depends closely on the bubble shape and decreases down to the breakdown voltage of gas at the normal boiling temperature or lower voltages. >

Power MOSFET failure revisited

Abstract: The failure of power MOSFETs during avalanche breakdown is discussed. A theory is presented that relates the failure to the temperature rise of the chip during the avalanche breakdown and to a critical current for failure. It is shown that the energy that can be safely dissipated during avalanche breakdown decreases as the starting current increases or as the case temperature increases. Thus, if power MOSFETs are to be rated for their energy dissipation capability during avalanche breakdown, both the starting current and temperature must be specified, since it is these two parameters that determine the failure limits, and not the energy. >

Self-aligned LDD lateral DMOS transistor with high-voltage interconnect capability

Abstract: Our invention is an annular-shaped or rectangular-shaped lateral DMOS device which overcomes the problems of field crowding caused by a high voltage drain interconnect line creating an increased electric field in the vicinity of a drift region/channel interface. To prevent the interconnect line voltage from causing field crowding, the drift region is discontinued for a portion under the interconnect line so as to make that part of the DMOS device inactive. Therefore, the portion of the DMOS device under the high voltage drain interconnect is not subject to field crowding and in no way reduces the breakdown voltage of the DMOS device. In one embodiment of this invention, a field oxide region is formed between a channel region and a drain region in an area under and extending out from under where a high voltage drain interconnect is to be formed. Impurities implanted in a subsequent impurity implant process to form the drift region will, therefore, be prevented from entering the silicon under the field oxide region.

Process of forming an isolation structure

Abstract: Two thin wedges of oxide extending along and from the boundaries of the field oxide layer without solution of continuity inside the substrate for a depth such as to separate dielectrically the region of silicon, present underneath the field oxide layer, having a doping level higher than the doping level of the bulk of the substrate and the regions of oppositely doped silicon in a MOS device allow obtaining simultaneously a high threshold voltage of the parasitic transistor, a high junction breakdown voltage and an excellent immunity to "Reach-through" between the depletion regions of uncorrelated junctions together with a reduced capacitance of the junctions and an improved geometry. Such wedges of oxide are obtained by means of deep anisotropic etch of silicon through a suitably exposed area, for example by means of an overetch of the nitride used for growing the thick oxide layer according to the known technique and by the subsequent filling of the deep etch with thermally grown silicon oxide.

Surge suppression on AC power lines

Abstract: A triggered surge suppression network is disclosed comprising a low voltage clamping device, a crowbar device and a trigger device. The voltage clamping device and the trigger device are connected in parallel; and these devices are connected in series to the crowbar device. The resulting circuit is connected across a voltage supply, in parallel to a load. The trigger device causes the crowbar device to break down at a pre-set value and discharge the energy of the surge through the low voltage clamping device. The breakdown voltage of the network will depend essentially on the breakdown voltage of the crowbar device while the peak voltage supplied to the load during the surge will independently be determined by the clamping voltage of the voltage clamping device.

Current-voltage characteristics of a high-current pulsed discharge in air

Abstract: The time-dependent arc voltage and resistance of a high-current pulsed discharge in air are obtained accurately by solving the circuit equation using the measured values of the current and breakdown voltage. Unipolar critically damped or overdamped pulsed discharges, with rise times of about 0.7 mu and peak currents in excess of 20 kA, are investigated. These discharges are characterized by four phases: initial phase, quasistationary phase, transient phase, and relaxation phase. The quasistationary phase occurs between the time of the current maximum and twice this time. The transient phase, which occurs after the quasistationary phase, corresponds to a negative slope of the V-I characteristic. The variable parameters were electrode separation, and gas pressure. The minimum arc resistance, at peak current, was about 50 m Omega . >

New varistor material

Abstract: A composite varistor material containing silicon carbide, a conductor, and an insulator has been developed. The material has rubberlike flexibility and is easily formed. A higher leakage resistivity (∼1012 Ω cm) and greater nonlinearity (∼10) than for silicon carbide varistors permit the material to be used as a gapless surge suppressor. The breakdown voltage (1–10 kV/cm) and other properties of the material vary with composition. High current capability (>200 A/cm2) and good energy absorption (>40 J/cm3) are obtained. Also, the material exhibits a low‐temperature coefficient (∼4×10−3/K) and a low dielectric constant (∼10) with no observed loss peak.

Catheter-mediated electrical ablation: the relation between current and pulse width on voltage breakdown and shock-wave generation.

Abstract: Voltage waveform breakdown is characteristic of barotraumatic shock-wave generation during electrical catheter ablation of cardiac arrhythmias. The purpose of this investigation was to avoid barotrauma by defining, in vitro, the limits of pulse amplitude and pulse width for rectangular constant-current pulses that do not result in voltage breakdown and subsequently to determine what pulsing frequency is safe for use when high-energy trains of pulses are used. Electric pulses were delivered with a variable waveform modulator with a wide dynamic range and bandwidth capable of delivering pulses of 30-10,000-mu sec duration with amplitudes of up to 25 A. Cathodal pulses were delivered to a 6F catheter immersed in fresh anticoagulated bovine blood warmed to 37 degrees C to stimulate the milieu of a catheter in the chambers of the human heart. The maximum pulse amplitude that could be delivered without incurring voltage waveform breakdown varied inversely with pulse duration. Pulses of 30 mu sec broke down at currents above 24 A (2,500 V). Pulses of 10,000-mu sec duration broke down at 1 A (250 V). The maximum safely delivered energy for a single pulse was 2.5 J for pulses of 80-120 mu sec. Peak power for single pulses was maximum at 50-55 kW with 30-50-mu sec pulses. Charge delivery for single pulses was maximized at 9 mC with long, 10,000-mu sec duration pulses. To deliver an electrical pulse with energy significantly greater than 2.5 J without incurring voltage breakdown, trains of pulses were delivered where each pulse in the train had previously been shown to be free of voltage breakdown.(ABSTRACT TRUNCATED AT 250 WORDS)

High-voltage TFT fabricated in recrystallized polycrystalline silicon

Abstract: High-voltage thin-film transistors (TFTs) fabricated using CW-Ar laser annealed polycrystalline silicon have an offset gate structure between the source and gate and between the gate and drain. The breakdown voltage, transconductance, and leakage current in various size TFTs are described. These TFTs exhibited n-channel enhancement characteristics with a low-threshold voltage, and a breakdown voltage above 100 V could be obtained at an offset gate length of 20 mu m. Active TFT circuits were fabricated with these high-voltage Si TFTs. These high-voltage TFT circuits can drive thin-film EL (electroluminescent display) at low signal voltage. >

On the calculation of breakdown voltages for uniform electric fields in compressed air and SF/sub 6/

Abstract: A novel method is described for calculating the breakdown voltage of uniform field gaps in compressed air and SF/sub 6/ without the need for experiments. This method is based on the criterion of self-recurring single-electron avalanches developed in the gap. It is shown that the results computed by this method for pd values to the right of Paschen's minimum (up to 15 kPa.m in air and up to 5 kPa.M in SF/sub 6/) are in good agreement with those measured experimentally. It is also shown that the use of the streamer criterion overestimates the breakdown voltage when applied for pd values where Townsend's mechanism is valid. In addition, it is shown that the size of the avalanche (and hence the parameter K) at breakdown is not constant as adopted in the literature; it depends upon the gap length and gas pressure. >

Resistorless electrostatic discharge protection device for high speed integrated circuits

Abstract: An electrostatic discharge protection circuit without the use of a series resistor is described. MOSFET transistors with a turn-on voltage above the postive supply voltage but below the breakdown voltage are used. In one embodiment, parasitic bipolar transistors formed in conjunction with the MOSFETs are employed for further protection.

An analytical and experimental investigation of the cutoff frequency f/sub T/ of high-speed bipolar transistors

Abstract: The effects of vertical and lateral structures on cutoff frequency and breakdown voltage are investigated for high-speed bipolar transistors. The cutoff frequencies are examined in the range from 2.5 to 80 GHz by analysis and from 3 to 20 GHz by experiment. To attain the maximum cutoff frequency, it is predicted that the collector width, the base width, and the collector concentration should be 0.12 mu m, 0.07 mu m, and 1.2*10/sup 16/ cm/sup -3/, respectively, and that in this scaled transistor, breakdown voltages, BV/sub CE0/ and BV/sub C8O/ should be reduced below 3 and 7.7 V respectively. >

Process and device performance of a high-speed double poly-Si bipolar technology using borosenic-poly process with coupling-base implant

Abstract: Use of boron and arsenic diffusions through an emitter polysilicon film (borosenic-poly emitter-base process) produces a transistor base width of less than 100nm with an emitter junction depth of 50 nm and an emitter-to-base reverse leakage current of approximately 70 pA. The borosenic-poly process resolves both the channeling and shadowing effects of a sidewall-oxided spacer during the base boron implantation. The process also minimizes crystal defects generated during the emitter and base implantations. The coupling-base boron implant significantly improves a wide variation in the emitter-to-collector periphery punchthrough voltage without degrading the emitter-to-base breakdown voltage current gain, cutoff frequency, or ECL gate delay time. A deep trench isolation with 4- mu m depth and 1.2- mu m width reduces the collector-to-substrate capacitance to 9 fF, while maintaining a transistor-to-transistor isolation voltage of greater than 25 V. The application of self-aligned titanium silicide technology to form polysilicon resistors without holes and to reduce the sheet resistance of the emitter and collector polysilicon electrodes to 1 Omega /square is discussed. >

Simple, very low dark current, planar long-wavelength avalanche photodiode

Abstract: We have demonstrated a novel planar, avalanche photodiode (APD) for use in long‐wavelength (0.95–1.65 μm) optical communication systems. The device is a separate absorption and multiplication region APD utilizing p+ guard rings which are concentric with, but not attached to the central diffused p+‐n junction region. Since no contact is made to the rings, their potential is allowed to ‘‘float’’ at a value somewhat less than that established by the externally applied voltage. The APD, which is fabricated in a manner identical to simple p‐i‐n photodiodes, eliminates edge breakdown effects while greatly reducing the electric field at the insulator/semiconductor interface. A 60‐μm‐diam junction device grown by vapor phase epitaxy is observed to have a primary dark current of <300 pA, and a capacitance of 290 fF at 90% of the breakdown voltage. Uniform gains as high as 11 have been observed.

Four-hundred-picosecond single-photon timing with commercially available avalanche photodiodes

Abstract: Avalanche photodiodes biased above the breakdown voltage are an interesting alternative to photomultiplier tubes in time‐correlated single‐photon counting. The characteristics and performance of a commercially available device (RCA C30921S) have been investigated. The time resolution is found to improve as the excess bias above the breakdown voltage is increased. Full width at half‐maximum values down to 400 ps have been measured with the detector cooled at −40 °C, and down to 460 ps at room temperature. The best results were obtained with an active quenching circuit, suitable for operation with excess bias voltage up to 40 V; at room temperature, fast gated operation was used for attaining optimum performance. Experimental data on the statistical behavior of the avalanche current pulses in these devices are reported and discussed.

Method of making symmetrical blocking high voltage breakdown semiconductor device

Abstract: A symmetrical blocking high breakdown voltage semiconductor device in which the lower junction termination is brought to the upper surface is fabricated by diffusing first and second regions of a first conductivity type into an upper surface of an epitaxial layer of a second conductivity type disposed on a substrate, and forming a groove having sloped sidewalls in the upper surface such that the groove extends through the second diffused region, the epitaxial layer and into the substrate. A thin layer of impurities of the first conductivity type is implanted into the sidewalls, and the impurities are electrically activated to form a low resistivity path that connects the substrate to the second diffused region. Subsequently, the semiconductor device may be separated from the wafer by cutting the wafer at the groove. The manufacturing process enables substantially complete fabrication of a plurality of devices while still in wafer form, thereby avoiding the inconvenience of processing individual dice.

Recovery of threshold voltage after hot-carrier stressing

Abstract: The recovery of threshold voltage due to high drain or gate voltage and the effects of hot-carrier stressing on the drain breakdown voltage of MOSFETs have been studied. A high oxide field causes slow recovery through tunneling detrapping of electrons in both p- and n-MOSFETs. For n-MOSFETs the mechanism of fast recovery is low-level hole injection at high V/sub D/. Hot-carrier stressing at high V/sub G/ causes the drain breakdown voltage to decrease (walk-in). This results in enhanced hold injection, thus increasing the rate of subsequent recovery of V/sub t/. The breakdown voltage increases and then decreases when stressed at low gate voltages. >

Inhomogeneous field breakdown in GIS-the prediction of breakdown probabilities and voltages. III. Discharge development in SF/sub 6/ and computer model of breakdown

Abstract: For pt.II see ibid., vol.3, no.3, p.931-8 (1988). Extensive investigations into various phases of discharge development in SF/sub 6/ (corona formation, streamer to leader transmission, leader, and propagation) are summarized, with the goal of familiarizing the engineer with the theoretical and empirical basis of a quantitative model SF/sub 6/ breakdown, including breakdown in highly inhomogeneous fields. The quantitative predictive capability of this model is tested for a number of examples, which demonstrate the correct prediction of geometry and pressure dependencies of the breakdown voltage. Combined with the modified volume-time 'law', the breakdown model becomes a valuable tool for the power engineer, capable of predicting statistical breakdown characteristics for a wide range of gap geometries and positive voltage waveforms as a function of pressure. The model does not cover negative polarity waveforms and becomes increasingly inaccurate as the waveform risetime increases over about 10 mu s. Future research planned to address both of these limitations and practical applications are outline. >

Process for forming an epitaxial layer having portions of different thicknesses

Abstract: An integrated circuit device uses a silicon chip having an epitaxial layer which has two portions of different thicknesses in which are formed separate junction transistors of different characteristics. In the growth of the epitaxial layer there is first formed on the front surface of the chip a localized sacrificial silicon dioxide layer removable in situ by baking in a reducing atmosphere. Then an epitaxial layer is grown by a first epitaxial deposition phase selectively over only the silicon dioxide free regions of the front surface of the chip. The sacrificial silicon dioxide layer is then removed in situ by baking in hydrogen. There is then resumed blanket growth of the epitaxial layer by a second epitaxial deposition phase. In the resulting chip, a large geometry junction transistor of relatively low switching speed and moderately high breakdown voltage (compared to 12 volts) is formed in the thicker epitaxial portion and a small geometry junction transistor of high switching speed and lower breakdown voltage is formed in the thinner epitaxial portion.

The effect of channel hot carrier stressing on gate oxide integrity in MOSFET

Abstract: The correlation between channel hot carrier stressing and gate oxide integrity is studied. It is found that channel hot carriers have no detectable effect on gate oxide integrity even when other parameters (e.g., Delta V/sub T/ and Delta VI/sub D/) have become intolerably degraded. In the extreme cases of stressing at V/sub G/ approximately=V/sub T/ with measurable hole injection current, however, the oxide charge-to-breakdown decreases linearly with the amount of hole fluence injected during the channel hot hole stressing. This may limit the endurance of a nonvolatile memory using hot holes for erasing. This can also explain the gate-to-drain breakdown of a device biased in the snap-back region, since snap-back at low gate voltage is favorable for hole injection. Snap-back-induced oxide breakdown could be an electrostatic-discharge failure mechanism. >