Showing papers on "Breakdown voltage published in 1991"

Semiconductor power devices with alternating conductivity type high-voltage breakdown regions

Abstract: A semiconductor power device wherein the reverse voltage across the p + -regions(s) and the n + -regions(s) is sustained by a composite buffer layer, shortly as CB-layer. The CB-layer contains two kinds of semiconductor regions with opposite types of conduction. These two kinds of regions are alternatively arranged, viewed from any cross-section parallel to the interface between the layer itself and the n + (or p + )-region. Whereas the hitherto-used voltage sustaining layer contains only one kind of semiconductor with single type of conduction in the same sectional view. Design guidelines are also provided in this invention. The relation between the on-resistance in unit area Ron and the breakdown voltage V B of the CB-layer invented is Ron ocV B 113 which represents a breakthrough to the conventional voltage sustaining layer, whereas the other performances of the power devices remain almost unchanged.

A low-voltage triggering SCR for on-chip ESD protection at output and input pads

Abstract: A novel silicon-controlled rectifier (SCR) structure for on-chip protection against electrostatic discharge (ESD) stress at output or input pads is presented. The SCR switches to an ON state at a trigger voltage determined by the gate length of an incorporated nMOS-like structure. Thus, the new SCR can be designed to consistently trigger at a voltage low enough to protect nMOS transistors from ESD. The capability of a protection circuit using the new SCR design is experimentally demonstrated. The tunability of the SCR trigger voltage with reference to the nMOS breakdown voltage is exploited to improve the human body model (HBM) ESD failure threshold of an output buffer from 1500 to 5000 V. >

Charging and flashover induced by surface polarization relaxation process

Abstract: Electric charges trapping into a dielectric medium are described from polarons trapped into sites which are characteristic of the material structure (polaron trap). In terms of susceptibility, that means charges are trapped into sites whose susceptibility is lower than their surrounding environment. The charge trapping produces polarization of the medium. The energy of polarization per embedded charge is estimated to be equal to 5χ (χ being the susceptibility). The surface breakdown of the dielectric is attributed both to charge detrapping and to relaxation of energy of polarization, using the collective many‐body process. The consequences of this interpretation are consistent with experiments on surface breakdown performed with a scanning electron microscope. Furthermore, considerations about the improvement of breakdown voltage for dielectric materials are introduced.

Realization of high breakdown voltage (>700 V) in thin SOI devices

Abstract: The avalanche breakdown voltage of silicon on insulator (SOI) lateral diodes is investigated theoretically and experimentally. Theoretically, a condition is derived for achieving a uniform lateral electric field and thus optimizing the breakdown voltage. Using this condition, it is shown that, for SOI thicknesses below about 1 mu m, diode breakdown voltage increases with decreasing SOI layer thickness. Experimentally, breakdown voltages in excess of 700 V have been demonstrated for the first time on diodes having approximately 0.1- mu m-thick SOI layers and 2- mu m-thick buried oxide layers. The results obtained demonstrate the feasibility of making high-voltage thin-film SOI LDMOS transistors and, more importantly, the ability to integrate such devices with high-performance ultra-thin SOI CMOS circuits on a single chip. >

Electric field effect in high Tc superconducting ultrathin YBa2Cu3O7−x films

Abstract: A multilayer high Tc superconducting field‐effect transistor‐like structure was made from ultrathin YBa2Cu3O7−x films. An epitaxially grown dielectric SrTiO3 insulation layer, which had a forward bias breakdown voltage of about 20 V, allowed an electric field induced change in the channel layer of 1.25×1013 carrier/cm2 per volt of the gate voltage. A significant modulation of the normal state and superconducting properties was observed in samples with YBa2Cu3O7−x channel layers of a few unit cells thick. By applying gate voltage of different polarities, Tc was both suppressed and enhanced by ∼1 K. The resistance was modulated by as much as 20% in the normal state and by over 1500% near the zero resistance temperature.

Extension of RESURF principle to dielectrically isolated power devices

Abstract: The RESURF (reduced surface field) principle has been extended to dielectrically isolated power devices including the effect of the formation of an inversion layer under the isolating oxide. Two device structures that allow high voltage operation have been investigated. Extensive two-dimensional simulations have been performed to relate the breakdown voltage to the doping and length of the drift region, and the thicknesses of the silicon layer and isolating oxide. It has been shown that lateral devices with breakdown voltages up to 600 V can be obtained. >

Breakdown voltage enhancement for devices on thin silicon layer/silicon dioxide film

Abstract: Studies of high-voltage lateral device structures on a thin silicon layer over silicon dioxide have been carried out. It was found both theoretically and experimentally that over 600-V devices can be realized using a structure consisting of an n diffusion layer over a 15- mu m-thick high-resistivity n/sup -/ silicon layer over 3- mu m silicon dioxide (SOI). A method is presented to enhance breakdown voltage by applying a large share of the voltage to the bottom oxide. >

Silicon carbide field-effect transistor with improved breakdown voltage and low leakage current

Abstract: A silicon carbide field-effect transistor is provided which includes a semiconductor substrate, a channel formation layer of silicon carbide formed above the substrate, source and drain regions provided in contact with the channel formation layer, a gate insulator disposed between the source and drain regions, and a gate electrode formed on the gate insulator, wherein a first contact between the channel formation layer and the drain region exhibits different electric characteristics from those of a second contact between the channel formation layer and the source region. Also provided is a method for producing such a silicon carbide field-effect transistor.

Gate breakdown in MESFETs and HEMTs

Abstract: A new model for gate breakdown in MESFETs and HEMTs is presented. The model is based upon a combination of thermally assisted tunneling and avalanche breakdown. When thermal effects are considered it is demonstrated that the model predicts increasing drain-source breakdown as the gate electrode is biased towards pinch-off, in agreement with experimental data. The model also predicts the gate current versus bias behavior observed in experimental data. The model is consistent with various reports of breakdown and light emission phenomena reported in the literature. >

High‐voltage 6H‐SiC p‐n junction diodes

Abstract: A chemical vapor deposition (CVD) process has been used to produce device structures of n- and p-type 6H-SiC epitaxial layers on commercially produced single-crystal 6H-SiC wafers. Mesa-style p-n junction diodes were successfully fabricated from these device structures using reactive ion etching, oxide passivation, and electrical contact metallization techniques. When tested in air, the 6H-SiC diodes displayed excellent rectification characteristics up to the highest temperature tested, 600 C. To observe avalanche breakdown of the p-n junction diodes, testing under a high-electrical-strength liquid was necessary. The avalanche breakdown voltage was 1000 V representing the highest reverse breakdown voltage to be reported for any CVD-grown SiC diode.

Semiconductor device on a dielectric isolated substrate

Abstract: The semiconductor device (34) comprising a semiconductor layer (23) forming a source region (25), a drain region (26), a channel region (27) and a lead-out region (28) is arranged on a thin semiconductor film insulator (22). For increasing the breakdown voltage between source and drain, which is smaller than in a device formed in a bulk silicon, due to holes generated by an impact ionization, the lead-out region (28) adjoined to the source region (25) and/or a further lead-out region adjacent to the drain region (26) are provided so as to reach the bottom of the insulator film (22). Excess holes primarily causes by said impact ionization are pulled off and removed very effectively via said lead-out region(s) thus increasing the breakdown voltage.

Two-dimensional analysis and design considerations of high-voltage planar junctions equipped with field plate and guard ring

Abstract: The breakdown voltages of planar junctions (both nonpunchthrough and punchthrough cases) equipped with field plates and guard rings are determined by evaluating the ionization integral using the potential distribution computed by solving Poisson's equation in two-dimensions by a finite difference method. The influence of various parameters, such as substrate doping concentration, n-layer thickness, field oxide thickness, cylindrical junction curvature, field plate width, and the spacing between field plate and guard ring, on the breakdown voltage is extensively studied. It is shown that an optimum value exists for the field oxide thickness to realize maximum breakdown voltage. The study also shows that the optimum oxide thickness depends upon cylindrical junction curvature, substrate doping concentration, and n-layer thickness. It is further shown that the permittivity of a passivant dielectric layer deposited over field plate structure influences the breakdown voltage when breakdown takes place at the field plate edge. The numerical results are compared with the experimental data, and good agreement between the two is observed. Based on this two-dimensional study, design guidelines are provided for achieving breakdown voltages close to maximum realizable values, by conserving the device area and reducing the ionization at the field plant edge. The results presented clearly demonstrate the superiority of the field plate design using punchthrough structures over nonpunchthrough structures in realizing a given breakdown voltage. >

Scaled dielectric antifuse structure for field-programmable gate array applications

Abstract: A scaled antifuse structure consisting of a nitride-oxide (NO) dielectric sandwiched between two polysilicon layers is presented. In addition to reducing the effective thickness of the antifuse dielectric, the current conduction asymmetry of the NO layer is also utilized to lower the breakdown voltage to 10.6 V, and consequently the programming voltage to 13.5 V, which is lower than that of previously reported antifuse structures. Time-dependent dielectric breakdown (TDDB) measurements verify that this scaled antifuse structure exhibits a lifetime exceeding ten years (>1*10/sup 12/ s) at 5.5 V in the unprogrammed state. Since a significant fraction of the total measured antifuse resistance is contributed by the sheet resistance of the polysilicon electrodes, this structure also demonstrates the reduction of this resistance component through silicidation of both top and bottom electrodes in the area outside of the antifuse. This poly-poly antifuse structure offers reduction in programmed voltage, reduction in silicon device area, simple peripheral circuitry design, and faster circuit operation due to lower capacitance than previous poly-N/sup +/ antifuse structures. >

Characterization of charge trapping and high-field endurance for 15-nm thermally nitrided oxides

Abstract: Device-quality gate oxides have been nitrided using both rapid thermal processing and conventional furnace treatment. Charge trapping and high-field endurance including breakdown field and time-dependent dielectric breakdown, are investigated in detail. It is found that proper nitridation can eliminate positive charge accumulation in oxides, increase charge to breakdown, suppress high-field injection-induced interface state generation, and decrease the dependence of the breakdown field on the gate area as a result of the reduced density of microdefects. Experimental results show that although both the density and capture cross-section of the bulk and interface traps increased by nitridation, the combined effects of bulk and interface traps induced by high-field injection can improve the stability of the flatband voltage. For lightly nitrided oxides, the trap generation rate is greatly decreased as compared with the as-grown oxide. Not only are the density and capture cross-section of the traps affected by nitridation, but also the locations of the trapped-charge centroids are changed. The experimental results for postnitridation annealing suggest that these property modifications most likely result from nitridation-induced structural changes rather than hydrogenation alone. >

Capacitively induced electrostatic discharge protection circuit

Abstract: An integrated circuit electrostatic discharge (ESD) protection circuit employs a capacitor and a zener diode to trigger a thick oxide ESD shunt field effect transistor (FET). When an ESD induced voltage at an input or output node reaches the turn-on voltage determined by the zener diode breakdown voltage, the shunting transistor is turned on by current capacitively coupled to the base of the parasitic bipolar transistor inherently formed in the thick oxide FET. The parasitic bipolar transistor is turned on in its saturated mode, substantially shorting the node to ground. At the end of the ESD event when the ESD induced current is no longer sufficient to keep the shunting transistor in its saturated mode, the shunting transistor turns off and the ESD protection circuit returns to its off mode, monitoring the input or output node for the occurrence of another ESD event.

High voltage pulse generation using current mode second breakdown in a bipolar junction transistor

Abstract: The characteristics of a bipolar junction transistor operating in the avalanche region and then triggered into current mode second breakdown are formulated If the time the BJT is subjected to secondary breakdown is limited the BJT may be used as a nanosecond, high voltage switch without sustaining damage Several methods of fast pulse generation, electrical and optical, using this mode of operation are discussed A 2000 V pulse generator, into 50 Ω, with a risetime of approximately 1 ns, jitter <100 ps, is then designed using these results

Influence of barriers on the lightning and switching impulse strength of mean air gaps in point/plane arrangements

Abstract: The influence of clean and polluted barriers on the breakdown voltage of point/plane mean air gaps (30 to 200 cm) under lightning and switching voltages is addressed. The conditions of existence of flashover around the barrier without breakdown and without surface discharge are determined. It is shown that a clean insulating barrier situated near the electrode point, particularly at about 20% of the gap, leads to a significant increase in the breakdown voltage of the air gap. This increase is especially due to channel elongation of the disruptive discharge. A polluted barrier with surface conductivity higher than 1.6 mu S leads, similar to a metallic barrier, to a decrease in the breakdown voltage as compared with that without a barrier. A simplified model to estimate the optimal position of the barrier, considering the surface charge densities on both of its sides, is presented. It gives results in good agreement with experimental ones. >

Semiconductor device having high breakdown voltage

Abstract: A p-type emitter layer 2 is formed in one surface portion of an n - -type base layer 1 of high resistance. p + -type contact layers 2b and n + -type current blocking layers 6 are formed in a preset area ratio in the surface area of the p-type emitter layer. A cathode electrode 4 is formed in contact with the contact layer 2b as well as the current blocking layer 6 of the pn junction diode section. With this cathode structure, the electron injection in the ON state can be suppressed so as to reduce the carrier concentration of a portion of the n - -type base layer 1 lying on the cathode side, and the parasitic transistor effect caused at the time of reverse recovery can be suppressed by provision of the current blocking layer 6.

Inhomogeneous Conductivity in Varistor Ceramics: Methods of Investigation

Abstract: The grain boundaries in zinc oxide ceramics exhibit different electrical behaviors. This results in separate paths of current flux through the microstructure and also in different breakdown voltages of each path. The paper describes some new methods for characterization of these paths. A galvanic determination is able to show the number of paths and their distribution across the varistor surface. The differences in breakdown voltage are visible using a line scan method. Current images in SEM can detect the paths of current along a varistor surface. Possible reasons for inhomogeneous current flux are inhomogeneous distribution of dopants, insufficient binder burnout, and pressing faults.

Study of the electric fields required for streamer propagation in humid air

Abstract: The electric field required to sustain streamer propagation is important to the interpretation of breakdown in nonuniform field geometries. Basic measurements of the minimum field for propagation have been carried out in uniform fields. These have shown that above a ‘threshold’ value of field, there is an increasing probability of propagation up to a ‘stability’ field at which propagation always occurs. Comparison is made (a) with earlier work in both uniform and nonuniform fields, (b) with a survey of the mean stresses required for breakdown under lightning impulse and steady voltages. This leads to the conclusions that the stability field is a better parameter to use than the threshold field in making comparisons with lightning impulse breakdown and that the threshold field corresponds more closely with the stress required for steady voltage breakdown. Humidity effects are discussed.

High voltage CMOS switch with protection against diffusion to well reverse junction breakdown

Abstract: A high voltage CMOS n-well switch with guarding against reverse junction breakdown, as well as gate-aided breakdown. The CMOS switch of the present invention comprises two pairs of cascoding p-channel MOSFET loads, two pairs of cascoding n-channel MOSFET drivers and an inverter for input. One device in each pair of MOSFETs is used as a guard against gate-aided breakdown. The p-channel MOSFETs have independent n-wells so that the guard devices have their n-wells independently biased without being pulled by the n-wells of the load devices. The inverter is used to provide complementary inputs to the switch. By having independent n-wells, the breakdown voltage of the switch is raised above p+/n-well reverse breakdown voltage.

InAlAs/InGaAs/InP HEMTs with high breakdown voltages using double-recess gate process

Abstract: The DC and RF performance of InAlAs/InGaAs/InP HEMTs fabricated using a double-recess gate process are reported. A gate-drain breakdown voltage as high as 16 V was observed. The HEMTs also exhibited a high sourcedrain breakdown voltage near pinchoff of 16 V and a low RF output conductance of 6mS/mm. For a 1.4 μm gate length, an intrinsic transconductance of 560 mS/mm and fr and fmax values of 16 and 40 GHz, respectively, were achieved.

Theoretical and experimental investigations on the process of high-pressure discharge development

Abstract: The voltage breakdown behavior of a plane-parallel gap of 0.48-mm length filled with helium was examined at atmospheric pressure with admixtures of dry air at relative pressures of 0, 10/sup -4/, 3*10/sup -4/, and 10/sup -3/. The initial stages of the breakdown were investigated by means of a quantitative model consisting of the electron, ion, and excited-particle conservation equations and the Poisson equation. The system of equations was solved for an applied voltage of 180 V, at one single partial pressure of the impurities. Two numerical routines were used for the solution: a commercial IMSL subroutine TWODEPEP, and a newly developed method of solution in several fractional steps. The results were compared and found to be in reasonable agreement although the new method indicated a somewhat slower rate of rise, particularly concerning electron density. The new method permits extension of the calculation up to electron densities equal to almost two orders of magnitude above the earlier limit. >

Scr protection structure and circuit with reduced trigger voltage.

Abstract: A low breakdown voltage device for protecting an integrated circuit from transient energy is disclosed This device provides an SCR having a reduced "snap-back" trigger voltage compatible with submicron integrated circuit fabrication processes A low breakdown voltage SCR protection circuit is also disclosed

High voltage lateral semiconductor device

Abstract: The present invention provides an improved lateral drift region for both bipolar and MOS devices where improved breakdown voltage and low ON resistance are desired. A top gate of the same conductivity type as the device region with which it is associated is provided along the surface of the substrate and overlying the lateral drift region. In an MOS device, the extremity of the lateral drift region curves up to the substrate surface beyond the extremity of the top gate to thereby provide contact between the JFET channel and the MOS channel.

Mos field effect transistor

Abstract: PROBLEM TO BE SOLVED: To achieve both increase of a breakdown voltage and decrease of on-resistance. SOLUTION: In this MOS field-effect transistor formed on a semiconductor substrate, and provided with a source N+ region 8, a body contact region 9, a gate region, a drift region and a drain N+ region 6, and in which the drift region is arranged between the drain N+ region 6 and the gate region, the gate region has a gate electrode 10 and a plurality of trenches 4 projecting from the gate electrode 10; in the drift region, the plurality of trenches 4 and one or more drift parts are alternately arranged; the gate electrode 10 has polysilicon densely doped in the inside; and each of the plurality of trenches 4 has a polysilicon electrode 5 thinly doped in the inside. COPYRIGHT: (C)2009,JPO&INPIT

Power transistor device having ultra deep increased concentration region

Abstract: A cellular insulated gate bipolar transistor ("IGBT") device employs increased concentration in the active region between spaced bases to a depth greater than the depth of the base regions. The implant dose which is the source of the increased concentration is about 3.5×1012 atoms per centimeter squared and is driven for about 10 hours at 1175° C. Lifetime is reduced by an increased radiation dose to reduce switching loss without reducing breakdown voltage or increasing forward voltage drop above previous levels. The increased concentration region permits a reduction in the spacing between bases and provides a region of low localized bipolar gain, increasing the device latch current. The avalanche energy which the device can successfully absorb while turning off an inductive load is significantly increased. The very deep increased conduction region is formed before the body and source regions in a novel process for making the new junction pattern.

Voltage collapse and transient energy function analyses of ac/dc systems

Abstract: This thesis presents a thorough analysis of saddle-node bifurcations for power system dynamic models, including a third order representation of high voltage direct current (HVDC) transmission, classic ac generator dynamics with reactive flows, and voltage and frequency dependent load models. Extensions of the Point of Collapse and Continuation methods, initially used in ac system voltage stability studies, are applied to the determination of these bifurcation points. These methods are compared and used for calculating bus voltage profiles (“nose” curves) and collapse points on ac/dc systems of up to 2158 buses, considering a variety of operational limits and controls, namely, ac/dc regulating transformer tap limits, voltage and reactive power limits, and area interchange control. AC generator reactive power limits, HVDC firing angle limits and voltage dependent current order limits (VDCOL) are shown to affect the stability and loadability of these systems. A vector Lyapunov function approach is employed to define a system wide energy function that can be used for stability analysis. This thesis describes the derivation of individual component Lyapunov functions for simplified models of HVDC links connected to “infinitely strong” ac systems, along with a standard ac Lyapunov function. Then, a novel method is proposed for obtaining the weighting coefficients

Characterization of bipolar snapback and breakdown voltage in thin-film SOI transistors by two-dimensional simulation

Abstract: A two-dimensional finite-difference simulator for silicon-on-insulator (SOI) MOSFETs is presented. The simulator is derived from the MINIMOS4 simulator and incorporates additional features which permit the characterization of the bipolar snapback effect, which has been observed as a limiting feature in ultra-thin-film transistors. The snapback effect is illustrated as a hysteresis mechanism whereby, for a given bias condition, there are two different solutions to the semiconductor equations, depending on the starting condition. Examples of the application of the simulator to predict breakdown voltage in submicrometer devices are considered. Excellent agreement with measured values of breakdown voltage has been achieved for submicrometer n-channel transistors, both with and without the use of lightly doped drains. >

Breakdown voltage in LDMOS transistors using internal field rings

Abstract: The optimization of the floating-ring parameters and the breakdown voltage of a lateral DMOS (LDMOS) transistor using a single floating ring is presented. A first-order analytical approach is presented, showing the upper limit of the position of the ring, with respect to the channel, and the doping concentration within the ring to increase the breakdown voltage. A 2D numerical calculation of the breakdown voltage and on-resistance of the LDMOS transistor is also presented. The results, which support the analytical approach, allow the use of simple design rules for the implementation of high-voltage LDMOS transistors on a thick epitaxial layer. It is shown that improvements of breakdown voltage is obtained if the distance between the channel and the field ring is equal to the field plate length and the doping concentration in the ring satisfies a specific relationship. With a single ring, the breakdown voltage increases from 170 to 280 V for the same device area and to over 480 V if the area is allowed to increase by 25%. >