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Showing papers on "Breakdown voltage published in 1999"


Proceedings ArticleDOI
L. Lorenz1, G. Deboy1, A. Knapp1, Martin Marz1
26 May 1999
TL;DR: The CoolMOS/sup TM/ as discussed by the authors, a new high voltage power MOSFET based on the concept of charge compensation, has been introduced, which shows both a very small input capacitance and a strongly nonlinear output capacitance.
Abstract: Recently, a new technology for high voltage power MOSFETs has been introduced: the CoolMOS/sup TM/. Based on the new device concept of charge compensation, the R/sub DS(on)/ area product for e.g. 600 V transistors has been reduced by a factor of 5. The devices show no bipolar current contribution like the well known tail current observed during the turn-off phase of IGBTs. CoolMOS/sup TM/ virtually combines the low switching losses of a MOSFET with the on-state losses of an IGBT. Furthermore, the dependence of R/sub DS(on)/ on the breakdown voltage has been redefined. The more than square-law dependence in the case of standard MOSFET has been broken and a linear voltage dependence achieved. This opens the way to new fields of application even without avalanche operation. System miniaturization, higher switching frequencies, lower circuit parasitics, higher efficiency, and reduced system costs are pointing the way towards future developments. Not only has the new technology achieved breakthrough at reduced R/sub DS(on)/ values, but new benchmarks have also been set for the device capacitances. Due to chip shrinkage and a novel internal structure, the technology shows both a very small input capacitance and a strongly nonlinear output capacitance. The drastically lower gate charge facilitates and reduces the cost of controllability, and the smaller feedback capacitance reduces the dynamic losses. With this new technology, the minimum R/sub DS(on)/ values in all packages are being redefined in the important 600-1000 V categories.

251 citations


Journal ArticleDOI
TL;DR: In this paper, the effects of surface defects on performance of kV-class 4H- and 6H-SiC epitaxial p-n junction diodes were investigated.
Abstract: Effects of surface defects on performance of kV-class 4H- and 6H-SiC epitaxial p-n junction diodes were investigated. The perimeter recombination and generation, instead of the bulk process, are responsible for forward recombination current and reverse leakage current of the diodes, respectively. Mapping studies of surface morphological defects have revealed that triangular-shaped defects severely degrade high-blocking capability of the diodes whereas shallow round pits and scratch give no direct impact. Device-killing defects in SiC epilayers are discussed based on breakdown voltage mapping. Effective minority carrier lifetimes are mainly limited not by bulk recombination but by perimeter recombination.

200 citations


Journal ArticleDOI
TL;DR: In this paper, the reverse breakdown voltage of p-GaN Schottky diodes was used to measure the electrical effects of high density Ar or H2 plasma exposure, and the damage depth was established as ∼400 A based on electrical and wet etch rate measurements.
Abstract: The reverse breakdown voltage of p-GaN Schottky diodes was used to measure the electrical effects of high density Ar or H2 plasma exposure. The near surface of the p-GaN became more compensated through introduction of shallow donor states whose concentration depended on ion flux, ion energy, and ion mass. At high fluxes or energies, the donor concentration exceeded 1019 cm−3 and produced p-to-n surface conversion. The damage depth was established as ∼400 A based on electrical and wet etch rate measurements. Rapid thermal annealing at 900 °C under a N2 ambient restored the initial electrical properties of the p-GaN.

190 citations


Journal ArticleDOI
TL;DR: In this article, high standoff voltage (450 V) Schottky rectifiers on hydride vapor phase epitaxy grown GaN on sapphire substrate were fabricated, including lateral geometry with rectangular and circular contacts.
Abstract: We fabricated high standoff voltage (450 V) Schottky rectifiers on hydride vapor phase epitaxy grown GaN on sapphire substrate. Several Schottky device geometries were investigated, including lateral geometry with rectangular and circular contacts, mesa devices, and Schottky metal field plate overlapping a SiO2 layer. The best devices were characterized by an ON-state voltage of 4.2 V at a current density of 100 A/cm2 and a saturation current density of 10^–5 A/cm2 at a reverse bias of 100 V. From the measured breakdown voltage we estimated the critical field for electric breakdown in GaN to be (2.2 ± 0.7) × 10^6 V/cm. This value for the critical field is a lower limit since most of the devices exhibited abrupt and premature breakdown associated with corner and edge effects.

158 citations


Journal ArticleDOI
TL;DR: In this paper, hole impact ionization coefficients have been accurately measured as a function of temperature in both 4H and 6H-SiC using the pulsed electron beam induced current (P-EBIC) technique.
Abstract: Hole impact ionization coefficients have been accurately measured as a function of temperature in both 4H and 6H-SiC using the pulsed electron beam induced current (P-EBIC) technique. For Chynoweth's equation ( α=a e − b / E ), our measurements gave an a p value of (2.6±0.12)×10 6 /cm and a b p value of (1.5±0.01)×10 7 V/cm for 6H-SiC at room temperature while the values of a p and b p for 4H-SiC were found to be (3.25±0.3)×10 6 /cm and (1.71±0.04)×10 7 V/cm, respectively, at room temperature. The coefficient a p was found to decrease with increasing temperature for both polytypes while the coefficient b p remained constant. Based upon this data, the breakdown voltage of the 4H and 6H-SiC devices is predicted to increase with temperature which is an important desirable characteristic for power devices.

136 citations


Patent
02 Apr 1999
TL;DR: An n-and p-type diffusion regions are formed in a region sandwiched between trenches arranged at a first main surface of a semiconductor substrate as mentioned in this paper, where a gate electrode layer is formed opposite to the p type well.
Abstract: An n type diffusion region and a p type diffusion region are formed in a region sandwiched between trenches arranged at a first main surface of a semiconductor substrate. A p type well is formed in the n- and p-type diffusion regions nearer the first main surface. A source n+ diffusion region is formed at the first main surface within the p type well. A gate electrode layer is formed opposite to the p type well sandwiched between the n type diffusion region and the source n+ diffusion region with a gate insulating layer disposed therebetween. The n- and p-type diffusion regions each have an impurity concentration distribution diffused from a sidewall surface of a trench. Thus, a fine, micron-order pn repeat structure can be achieved with sufficient precision and a high breakdown voltage semiconductor device is thus obtained which has superior on-state voltage and breakdown voltage as well as fast switching characteristics.

105 citations


Journal ArticleDOI
TL;DR: In this article, a numerical model for obtaining linear doping profiles in the drift region of high-voltage thin-film SOI devices is proposed and experimentally verified, and the dependence of the breakdown voltage on the doping density and doping concentration slope in the linearly doped drift region is also investigated experimentally.
Abstract: A numerical model for obtaining linear doping profiles in the drift region of high-voltage thin-film SOI devices is proposed and experimentally verified. Breakdown voltage in excess of 612 V on LDMOS transistors with 0.15-/spl mu/m SOI layer, 2-/spl mu/m buried oxide, and 50-/spl mu/m drift region is designed and demonstrated using this model. Theoretical and experimental dependence of the breakdown voltage on the drift region length are compared. Good agreement between the simulation and experimental results are obtained. Dependence of the breakdown voltage on the doping density and doping concentration slope in the linearly doped drift region is also investigated experimentally. Results indicate that an optimum concentration slope is needed in order to optimize the breakdown voltage in the thin-film SOI devices with a linear doping drift region. Finally, a 600-V CMOS compatible thin-film SOI LDMOS process is also described.

88 citations


Proceedings ArticleDOI
Minoru Sakata1, Y. Komura, Tomonori Seki, K. Kobayashi, K. Sano, S. Horiike 
01 Jan 1999
TL;DR: In this paper, a single crystal silicon based electrostatic actuator is presented, which is fabricated by critical-dimensions-controllable SOI-A/B (Anodic bonding) process.
Abstract: A MMR which utilizes a single crystal silicon based electrostatic actuator is presented in this paper. The MMR is fabricated by critical-dimensions-controllable SOI-A/B (Anodic bonding) process. Size of the MMR is 2.0 mm/spl times/2.5 mm and driving voltage is 24 V. Hot-switching tests with 10 V-10 mA resistive load were performed 10/sup 6/ cycles with around 0.5 ohm relay resistance (sum. of signal line resistance, contact resistance and package resistance). Breakdown voltage (stand off voltage) is larger than 200 V. Switching time was around 03 msec and power consumption was less than 0.05 mW.

81 citations


Journal ArticleDOI
TL;DR: In this article, the authors studied on-state and off-state breakdown of Ga/sub 0.53/As/InP composite-channel HEMT's with variable GaInAs channel thickness of 30, 50, and 100 /spl Aring.
Abstract: Short-channel Ga/sub 0.47/In/sub 0.53/As high electron mobility transistors (HEMTs) suffer from low breakdown voltages due to enhanced impact-ionization effects in the narrow bandgap channel. This could limit the application of single-channel devices to medium power millimeter-wave systems. A composite Ga/sub 0.47/In/sub 0.53/As/InP channel, which exploits the high electron mobility of Ga/sub 0.47/In/sub 0.53/As at low electric fields, and the low impact-ionization and high electron saturation velocity of InP at high electric fields can overcome this limitation. In this paper we study on-state and off-state breakdown of Ga/sub 0.47/In/sub 0.53/As/InP composite-channel HEMT's with a variable GaInAs channel thickness of 30, 50, and 100 /spl Aring/. Reduction of channel thickness leads to the improvement of both on-state and off-state breakdown voltages. In on-state conditions, the enhancement in the effective Ga/sub 0.47/In/sub 0.53/As channel bandgap that takes place when the channel thickness is reduced to the order of the de Broglie wavelength (channel quantization) effectively enhances the threshold energy for impact-ionization, which is further reduced by real space transfer of electrons from the Ga/sub 0.47/In/sub 0.53/As into the wider bandgap InP. Channel thickness reduction also causes a decrease in the sheet carrier concentration in the extrinsic gate-drain region and therefore, a reduction of the electric field beneath the gate. This, together with the adoption of an Al/sub 0.6/In/sub 0.4/As Schottky layer (increasing the gate Schottky barrier height), leads to excellent values of the gate-drain breakdown voltage. In conclusion, composite channel InAlAs/GaInAs/InP HEMTs, thanks to the combined effect of effective band-gap increase, enhanced real space transfer into InP, and sheet carrier density reduction, allow a good trade-off between current driving capability and both on-state and off-state breakdown voltage.

78 citations


Journal ArticleDOI
TL;DR: In this article, the analysis of spherical conducting particle motion as well as particle initiated breakdown in electric fields between diverging conducting plates with dc voltage in atmospheric air is discussed, where the particle is placed on the horizontal electrode surface where the electric field is nearly equal to the lifting field, the particle progresses towards a higher electric field region by the effect of Coulomb force and electrical gradient force.
Abstract: This paper deals with the analysis of spherical conducting particle motion as well as particle initiated breakdown in electric fields between diverging conducting plates with dc voltage in atmospheric air. Motion of spherical particle was estimated by solving the motion equation numerically, and the results agreed well with the experimental ones. It was found that when the particle is placed on the horizontal electrode surface where the electric field is nearly equal to the lifting field, the particle progresses towards a higher electric field region by the effect of Coulomb force and electrical gradient force. This is true for a nonspherical conducting particle. The obtained results for particle motion suggest that much attention should be paid in the design of GIS particle traps to forces acting on the particle directly towards the higher electric field region. Moreover, the particle-initiated breakdown is discussed on the basis of the experimental and theoretical results. It was found that one of the reasons for reduction of the breakdown voltage is the effect of microdischarge between the particle and an oppositely charged electrode.

77 citations


Patent
03 Mar 1999
TL;DR: In this article, a high-voltage edge termination for planar structures which comprise a semiconductor body (1 to 4) of a first conduction type was proposed, where the floating regions are separated from one another in such a way that the zones between them are cleared when a voltage which is lower in comparison to the breakdown voltage is applied to the floating region (5, 15, 25).
Abstract: The invention relates to a high-voltage edge termination for planar structures which comprise a semiconductor body (1 to 4) of a first conduction type At least one of the magnetoresistors (7, 17) which is separated from the semiconductor body by an insulating layer (9) is provided on the same in the edge area thereof Floating regions (5, 15, 25) of the second conduction type are provided in the edge area of the semiconductor body (1 to 4) The floating regions are separated from one another in such a way that the zones between the floating regions (5, 15, 25) are cleared when a voltage which is lower in comparison to the breakdown voltage of the semiconductor body (1 to 4) is applied to the floating regions (5, 15, 25)

Journal ArticleDOI
TL;DR: An empirical one parameter-based power law model for leakage current through one or more soft breakdown spots in ultrathin gate oxides is presented in this article, which can be obtained in nearly five decades of current from 0.5 to 5 V. In addition, there exists a slight correlation between the parameters which describe the soft breakdown conduction characteristic and the stressing condition which triggers it.
Abstract: An empirical one parameter-based power law model for the leakage current through one or more soft breakdown spots in ultrathin (<5 nm) gate oxides is presented. Good fit to data can be obtained in nearly five decades of current from 0.5 to 5 V. In addition, it is shown that there exists a slight correlation between the parameters which describe the soft breakdown conduction characteristic and the stressing condition which triggers it.

Proceedings ArticleDOI
14 Jun 1999
TL;DR: In this paper, a systematic study of oxide reliability in the thickness range 13.8 nm to 2.8nm is presented, where it is demonstrated that the time-to-breakdown should be extrapolated as a function of gate voltage for sub-5 nm oxides, and that the temperature acceleration increases with decreasing thickness.
Abstract: A systematic study of oxide reliability is presented in the thickness range 13.8 nm to 2.8 nm. It is demonstrated that (i) the time-to-breakdown should be extrapolated as a function of gate voltage for sub-5 nm oxides, (ii) the temperature acceleration of time-to-breakdown increases drastically with decreasing thickness, and (iii) the combination of increased temperature acceleration, area scaling and low percentage failure rates leads to marginal intrinsic reliability for ultra-thin oxides, severely limiting further downscaling of oxide thickness.

Journal ArticleDOI
TL;DR: In this paper, the effect of nonsinusoidal voltage, i.e. voltage affected by the presence of harmonics, on intrinsic aging of cable and capacitor insulating materials, such as cross-linked polyethylene (XLPE) and polypropylene (PP), was investigated.
Abstract: This paper investigates the effect of nonsinusoidal voltage, i.e. voltage affected by the presence of harmonics, on intrinsic aging of cable and capacitor insulating materials, i.e. cross-linked polyethylene (XLPE) and polypropylene (PP). The results of life tests under sinusoidal and distorted voltage, the latter obtained superimposing one or more harmonics on the 50 Hz component, are processed by statistical techniques derived from design-of-experiment procedures. It is shown that the factor predominant on aging acceleration due to the voltage distortion is voltage-peak increase, but also waveform slope and voltage rms value have statistical significance. Life models are obtained for XLPE and PP insulating materials, which show the endurance of the two materials to aging under nonsinusoidal conditions.

Journal ArticleDOI
TL;DR: In this paper, the conditions for the onset of streamers in such laser-produced plasmas, both experimentally and through numerical simulations, were studied, demonstrating the importance of the electron density and its gradient on the generation of streamer.
Abstract: In an ongoing program using ultrashort laser pulses to provoke discharges in air over considerable distances at electric fields below breakdown threshold, we have studied the conditions for the onset of streamers in such laser-produced plasmas, both experimentally and through numerical simulations. The results demonstrate the importance of the electron density and of its gradient on the generation of streamers. Also, a significant reduction of the breakdown voltage for a 30 cm plane-plane gap in air was observed with a laser pulse energy of 15 mJ. Finally, a direct comparison of laser-induced breakdown in air and in nitrogen shows the influence of electron attachment to oxygen on the discharge process.

Journal ArticleDOI
S. Merchant1
TL;DR: In this paper, a simple analytical model for the electric field distribution in silicon-on-insulator (SOI) reduced surface field (RESURF) structures is developed, which applies for uniform and linearly graded doping profiles.
Abstract: A simple analytical model for the electric field distribution in silicon-on-insulator (SOI) reduced surface field (RESURF) structures is developed. The model applies for uniform and linearly graded doping profiles. It is also applicable to trench MOS barrier Schottky (TMBS) rectifiers, which have a similar structure. The results are valuable for breakdown voltage, tunneling, hot carrier, and other electric field dependent analyses.

Journal ArticleDOI
T. Tomita1, H. Utsunomiya1, T. Sakura1, Yoshinari Kamakura1, Kenji Taniguchi1 
TL;DR: In this paper, the authors investigated the soft breakdown properties of thin gate oxide films using a constant current stress measurement and showed that all types of breakdown originate from the same precursor and the magnitude of the following local heating due to the transient current in a conductive micro spot determines the charge conduction properties after a breakdown event.
Abstract: Soft breakdown properties of thin gate oxide films are investigated using a constant current stress measurement. The soft breakdown can be classified into two different modes from the current conduction characteristics of post breakdown oxides: one of the modes shows a telegraph switching pattern and the other random noise. The generation probabilities of two soft breakdown modes and hard breakdown strongly depend on the stress current. Time-to-breakdown is well characterized by a universal function of stress conditions regardless of the breakdown modes. These experimental findings imply that all types of breakdown originate from the same precursor and the magnitude of the following local heating due to the transient current in a conductive micro spot determines the charge conduction properties after a breakdown event.

Journal ArticleDOI
TL;DR: In this paper, the breakdown effect of dielectric material at voltages of the order of 1 V was investigated by means of voltage ramp experiments on a series of nominally identical Co/Al2O3/Co tunnel junctions.
Abstract: Due to their very thin tunnel barrier layer, magnetic tunnel junctions show dielectric breakdown at voltages of the order of 1 V. At the moment of breakdown, a highly conductive short is formed in the barrier and is visible as a hot spot. The breakdown effect is investigated by means of voltage ramp experiments on a series of nominally identical Co/Al2O3/Co tunnel junctions. The results are described in terms of a voltage dependent breakdown probability, and are further analyzed within the framework of a general model for the breakdown probability in dielectric materials, within which it is assumed that at any time the breakdown probability is independent of the (possibly time-dependent) voltage that has been previously applied. The experimental data can be described by several specific forms of the voltage breakdown probability function. A comparison with the models commonly used for describing thin film SiO2 breakdown is given, as well as suggestions for future experiments.

Proceedings ArticleDOI
T. Pompl1, Helmut Wurzer, M. Kerber, R.C.W. Wilkins, I. Eisele 
23 Mar 1999
TL;DR: In this article, the degradation of important transistor parameters related to soft breakdown and hard breakdown were studied, where long and short channel transistors were homogeneously stressed at elevated temperature until soft breakdown or hard breakdown occurred.
Abstract: The degradation of important transistor parameters related to soft breakdown and hard breakdown were studied. Long and short channel transistors were homogeneously stressed at elevated temperature until soft breakdown or hard breakdown occurred. The only noticeable signature of soft breakdown is an increase in off current due to enhanced gate induced drain leakage current. This effect arises if the soft breakdown is located within the gate-to-drain overlap region. Soft breakdown generates a spot or path of negative charges in the oxide and therefore enhances gate induced drain leakage current.

01 Jan 1999
TL;DR: In this paper, the authors carried out a systematic study of on-state breakdown in a sample set of InAlAs/InGaAs HEMT's using a new gate current extraction technique in conjunction with sidegate and temperature-dependent measurements.
Abstract: We have carried out a systematic study of on- state breakdown in a sample set of InAlAs/InGaAs HEMT's using a new gate current extraction technique in conjunction with sidegate and temperature-dependent measurements. We find that as the device is turned on, the breakdown voltage limiting mechanism changes from a TFE-dominated process to a multiplication-dominated process. This physical understanding allows the creation of a phenomenological physical model for breakdown which agrees well with all our experimental results, and explains the relationship between and the sheet carrier concentration. Our results suggest that depending on device design, either on-state or off-state breakdown can limit maximum power.

Journal ArticleDOI
TL;DR: In this article, the substrate bias effect and source-drain breakdown characteristics in body-tied short-channel silicon-on-insulator metal oxide semiconductor field effect transistors (SOI MOSFET's) were investigated.
Abstract: The substrate-bias effect and source-drain breakdown characteristics in body-tied short-channel silicon-on-insulator metal oxide semiconductor field effect transistors (SOI MOSFET's) were investigated. Here, "substrate bias" is the body bias in the SOI MOSFET itself. It was found that the transistor body becomes fully depleted and the transistor is released from the substrate-bias effect, when the body is reverse-biased. Moreover, it was found that the source-drain breakdown voltage for reverse-bias is as high as that for zero-bias. This phenomenon was analyzed using a three-dimensional (3-D) device simulation considering the body-tied SOI MOSFET structure in which the body potential is fixed from the side of the transistor. This analysis revealed that holes which are generated in the transistor are effectively pulled out to the body electrode, and the body potential for reverse-bias remains lower than that for zero-bias, and therefore, the source-drain breakdown characteristics does not deteriorate for reverse-bias. Further, the influence of this effect upon circuit operation was investigated. The body-tied configuration of SOI devices is very effective in exploiting merits of SOI and in suppressing the floating body-effect, and is revealed to be one of the most promising candidates for random logic circuits such as gate arrays and application specific integrated circuits.

Journal ArticleDOI
Dethard Peters1, R. Schorner1, Peter Friedrichs1, J. Volkl1, H. Mitlehner1, D. Stephani1 
TL;DR: In this paper, a SiC triple ion implanted MOSFET with a blocking voltage of 1800 V has been fabricated by applying a novel processing scheme, n/sup +/ source regions, p-base regions and p-wells.
Abstract: 6H silicon carbide vertical power MOSFETs with a blocking voltage of 1800 V have been fabricated. Applying a novel processing scheme, n/sup +/ source regions, p-base regions and p-wells have been fabricated by three different ion implantation steps. Our SiC triple ion implanted MOSFETs have a lateral channel and a planar polysilicon gate electrode. The 1800 V blocking voltage of the devices is due to the avalanche breakdown of the reverse diode. The reverse current density is well below 200 /spl mu/A/cm/sup 2/ for drain source voltages up to 90% of the breakdown voltage. The MOSFETs are normally off showing a threshold voltage of 2.7 V. The active area of 0.48 mm/sup 2/ delivers a forward drain current of 0.3 A at Y/sub GS/=10 V and V/sub DS/=8 V. The specific on resistance was determined to 82 m/spl Omega/dcm/sup 2/ at 50 mV drain source voltage and at V/sub GS/=10 V which corresponds to an uppermost acceptable oxide field strength of about 2.7 MV/cm. This specific on resistance is an order of magnitude lower than silicon DMOSFET's of the same blocking capability could offer.

Patent
Jenoe Tihanyi1
08 Dec 1999
TL;DR: In this article, a highvoltage edge termination structure for planar structures is proposed, where the edge area of the semiconductor body is provided with floating regions of a second conductivity type.
Abstract: A high-voltage edge termination structure for planar structures. The planar structures have a semiconductor body of a first conductivity type whose edge area is provided with at least one field plate isolated from the semiconductor body by an insulator layer. The edge area of the semiconductor body is provided with floating regions of a second conductivity type. The floating regions are spaced at such a distance from one another that zones between the floating regions are depleted even at an applied voltage which is low in comparison with a breakdown voltage of the semiconductor body for the floating regions.

Journal ArticleDOI
L.F. Eastman1
TL;DR: In this paper, the frequency response and drain-source breakdown voltage have been determined experimentally and the average electron transit velocity, determined from cut-off frequency, is 1.2 × 107 cm/s and the breakdown electric field is estimated to be 3 MV/cm.
Abstract: The fabrication of AlGaN/GaN high electron mobility transistors (HEMTs) employs strong spontaneous and piezoelectric polarization. The material was grown by OMVPE at 1050 °C and 75 Torr. The Hall measurements yielded ≈1 × 1013/cm2 electron sheet density, with 1200 to 1600 cm2/Vs electron mobility for 300 A Al0.3Ga0.7N/GaN on sapphire at 300 K. The process steps for mesa isolation, Ohmic and Schottky contacts are presented. The frequency response and drain–source breakdown voltage have been determined experimentally. The average electron transit velocity, determined from cut-off frequency, is 1.2 × 107 cm/s, and the breakdown electric field is estimated to be 3 MV/cm. On sapphire substrates, large periphery devices yielded 1.8 W/mm at 78% power-added efficiency and small periphery devices yielded 3.3 W/mm at 36% power-added efficiency at 4 GHz. Performance limitations due to electron trapping during HEMT operation are included. Predictions of >20 W/mm microwave output power are presented for these devices on SiC substrates.

Patent
17 Sep 1999
TL;DR: In this article, a high conductive region 18, constituting a surface part of a drain region is diffused more deeply than a main diffused layer 36 and a channel diffusion layer 37 for reducing the resistance.
Abstract: PROBLEM TO BE SOLVED: To provide a high breakdown voltage having low continuity resistance. SOLUTION: A high conductive region 18, constituting a surface part of a drain region is diffused more deeply than a main diffused layer 36 and a channel diffusion layer 37 for reducing the resistance. Furthermore, the high conductive region 18 is enclosed by a P-type diffused region 40 having no ball- like junctions, and a depleted layer expanding to the high conductive region 18 expands toward the inside of the high conductive region 18. Accordingly, low resistance is maintained, while high breakdown voltage is maintained.

Journal ArticleDOI
TL;DR: In this paper, the state of knowledge regarding the physics of breakdown voltage in InP HEMTs, placing it in contrast with GaAs PHEMTs and the current understanding regarding burnout, a closely related phenomenon.
Abstract: In spite of their outstanding transport characteristics, InP high-electron mobility transistors (HEMTs) deliver lower output power than GaAs pseudomorphic HEMTs (PHEMTs) throughout most of the millimeter-wave regime. However, the superior power-added efficiency of InP HEMTs when compared with GaAs PHEMTs makes this technology attractive for many applications. The reason for the relatively inferior power output of InP HEMTs lies in their comparatively small off-state and on-state breakdown voltages. This paper reviews the state of knowledge regarding the physics of breakdown voltage in InP HEMTs, placing it in contrast with GaAs PHEMTs. It also presents current understanding regarding burnout, a closely related phenomenon. This paper concludes by discussing strategies for improving the breakdown voltage and the power output of InP HEMTs.

Proceedings ArticleDOI
24 May 1999
TL;DR: In this article, high density metal-insulator-metal capacitors with capacitance densities of 1.0 to 2.0 fF/m/sup 2/ using PECVD nitride dielectric have been integrated for the first time into the backend metallization layers of a 0.25 /spl mu/m CMOS process flow.
Abstract: High density metal-insulator-metal capacitors with capacitance densities of 1.0 to 2.0 fF//spl mu/m/sup 2/ using PECVD nitride dielectric have been integrated for the first time into the backend metallization layers of a 0.25 /spl mu/m CMOS process flow. Capacitor breakdown voltage, linearity and reliability meet mixed-signal circuit requirements with less than 0.1% 3-sigma percentage matching for a 0.225 pF capacitor. Less than 0.6 defects/cm/sup 2/ has been achieved for 2.0 fF//spl mu/m/sup 2/ capacitance density. Q>80 at 2 GHz was measured, indicating its usefulness in RF applications.

Proceedings ArticleDOI
06 Sep 1999
TL;DR: In this paper, a new compact model for the impactionization coefficient is proposed, which nicely fits the theoretical data from the Boltzmann solver HARM and the available experimental data in the above temperature range.
Abstract: In this work, electron impact-ionization in silicon is investigated both theoretically and experimentally in the temperature range between 25 and 400/spl deg/C. A new compact model for the impact-ionization coefficient is proposed, which nicely fits the theoretical data from the Boltzmann solver HARM and the available experimental data in the above temperature range. The new model has been validated by simulating the reverse characteristics of junction diodes, and turns out to correctly predict the temperature dependence of breakdown voltage.

Patent
13 Jul 1999
TL;DR: In this paper, a drift region of first conductivity type is provided in the semiconductor substrate and the drift region extends through the opening in the buried electrically insulating layer.
Abstract: Power semiconductor devices include a semiconductor substrate having a face thereon and a buried electrically insulating layer extending laterally in the semiconductor substrate and having an opening therein. A drift region of first conductivity type is also provided in the semiconductor substrate. To improve breakdown voltage characteristics, the drift region extends through the opening in the buried electrically insulating layer and has a first conductivity type doping concentration therein that is established at a level sufficient to generate a first conductivity type charge density of between 1×10 12 cm -2 and 5×10 13 cm -2 across the opening.

Journal ArticleDOI
TL;DR: In this paper, the breakdown voltage, transconductance and cutoff frequency of zincblende phase GaN MESFET devices were analyzed using a full band, ensemble Monte Carlo simulation.
Abstract: In this paper, we present the first theoretical study of the breakdown properties of zincblende phase GaN MESFET devices. The calculations are made using a full band, ensemble Monte Carlo simulation that includes a numerical formulation of the impact ionization transition rates. The breakdown voltage, transconductance and cutoff frequency are calculated for the GaN MESFET under two different conditions, with and without semiconductor-oxide interface states. Uniform surface depletion regions model the effect of the interface states. It is found that the breakdown voltage of the zincblende GaN MESFET is less dependent upon the surface depletion conditions than a corresponding GaAs MESFET. It is also found that the drain current increases more gradually with increasing drain-source voltage at the onset of breakdown and that the breakdown voltage of the zincblende GaN MESFET is predicted to be several times larger than that of a comparable GaAs MESFET. The maximum current gain cutoff frequency of a 0.1 /spl mu/m gate length GaN MESFET is calculated to be 230 and 220 GHz, for the non-surface-depleted and the surface depleted devices respectively.