Showing papers on "Breakdown voltage published in 2003"

High breakdown voltage AlGaN-GaN power-HEMT design and high current density switching behavior

Abstract: AlGaN-GaN power high-electron mobility transistors (HEMTs) with 600-V breakdown voltage are fabricated and demonstrated as switching power devices for motor drive and power supply applications. The fabricated power HEMT realized the high breakdown voltage by optimized field plate technique and the low on-state resistance of 3.3 m/spl Omega/cm/sup 2/, which is 20 times lower than that or silicon MOSFETs, thanks to the high critical field of GaN material and the high mobility in 2DEG channel. The fabricated devices also demonstrated the high current density switching of 850 A/cm/sup 2/ turn-off. These results show that AlGaN-GaN power-HEMTs are one of the most promising candidates for future switching power device for power electronics applications.

Exceptionally high voltage Schottky diamond diodes and low boron doping

Abstract: Exceptionally pure epitaxial diamond layers have been grown by microwave plasma chemical vapour deposition, which have low boron doping, from 5 × 1014 to 1 × 1016 cm−3, and the compensating n-type impurities are the lowest reported for any semiconducting diamond, 700 °C for ~1 s in air. Schottky diodes made on these epitaxial diamond films have breakdown voltages >6 kV, twelve times the highest breakdown voltage reported for any diamond diode and higher than any other semiconductor Schottky diode.

Electrical breakdown and ESD phenomena for devices with nanometer-to-micron gaps

Abstract: The current vs. voltage and electrical breakdown behavior for devices with micron and sub-micron gaps between conductors is studied. The limitations of the well-known but often-misinterpreted Paschen curve are discussed. The little-known modified Paschen curve, that includes field emission effects so important in understanding breakdown behavior for devices with sub-micron gaps, is described. Current vs. voltage measurements across metal-air-metal, metal-insulator-metal and metal-insulator-air-insulator-metal gaps with gaps ranging from 4 nm to 4 μm are reported. The breakdown voltage for an air gap of 0.9 μm was found to be 150 V, far below the Paschen curve minimum breakdown limit, and field emission behavior was confirmed via the Fowler-Nordheim plot. Metal-insulator-metal gaps with a diamond-like carbon thin-film with a thickness of 4 nm had a breakdown voltage of only 1V. SEM and AFM analysis show that the breakdown damage is crater-like and through the carbon layer. Other characterization of the damage caused by breakdown is presented. Tribocharging, electrostatic induction, and other ESD-related phenomena, are discussed for several devices with sub-micron gaps. It is concluded that devices with sub-micron gaps can face a serious challenge due to electrical breakdown during manufacturing, handling and operation. These devices include photolithographic reticles, magnetic recording heads, MEMS and field emission displays.

Super-junction LDMOST on a silicon-on-sapphire substrate

Abstract: A super-junction lateral double diffused MOST (SJ-LDMOST) in silicon-on-sapphire technology, targeting power integrated circuits (PICs), is proposed, implemented and characterized. The proposed structure eliminates "substrate-assisted-depletion" effects in lateral SJ devices thus achieving charge compensation between the n and p SJ-pillars as well as a uniform electric field distribution in the drift region in the off-state. Three-dimensional (3-D) simulations of the device, using realistic aspect ratios for the SJ-pillars, indicate that a significant reduction in specific on-resistance for a given breakdown voltage can be achieved as compared to conventional reduced surface field (RESURF) devices. Experimental devices were implemented using a seven mask CMOS compatible process. Fabricated SJ-LDMOSTs with a drift region length of 66 /spl mu/m and a pillar aspect ratio of 1.2 /spl mu/m/0.7 /spl mu/m (width/height) exhibit a specific on-resistance of 0.82 /spl Omega/.cm/sup 2/ and a breakdown voltage (BV) ranging between 500 and 600 V corresponding to less than 8.5% charge imbalance in the pillars.

LDMOS transistors and methods for making the same

Abstract: LDMOS transistor devices and fabrication methods are provided, in which additional dopants are provided to region of a substrate near a thick dielectric between the channel and the drain to reduce device resistance without significantly impacting breakdown voltage. The extra dopants are added by implantation prior to formation of the thick dielectric, such as before oxidizing silicon in a LOCOS process or following trench formation and before filling the trench in an STI process.

Breakdown processes in metal halide lamps

Abstract: Metal halide lamps typically have cold fills of tens to a few hundred Torr of a rare gas and the vapour from the dosing of a metal halide solid and mercury. Breakdown and starting of the lamp occurs following application of multi-kV pulses across electrodes separated by a few centimetres. Restarting of warm lamps is often problematic as the available voltage is insufficient to break down the higher pressure (>many atm) of metal halide vapour. In this paper, fundamental processes during breakdown in cold and warm, idealized metal halide lamps in mixtures of Ar and Hg are investigated using a two-dimensional fluid model for plasma transport. We find that the capacitances of the walls of the discharge tube and adjacent ground planes are important in determining the breakdown voltage and avalanche characteristics. The prompt capacitance represented by, for example, external trigger wires provides a larger E/N to sustain ionization early in the avalanche. This effect is lost as the walls charge and shield the plasma from the ground planes. More rapid breakdown occurs in slightly warm lamps having small vapour pressures of Hg due to the resulting Penning mixture. Warmer lamps, having larger mole fractions of Hg, have less efficient breakdown as the increase in momentum transfer of the electrons is not offset by the additional ionization sources of the Penning mixture.

On the destruction limit of Si power diodes during reverse recovery with dynamic avalanche

Abstract: The reverse recovery destruction limit of 3.3 kV fast recovery diodes was investigated by measurements and device simulations. Based on a good agreement between the measured destruction limit and current filamentation in simulations, it is proposed that the destruction is triggered by the onset of impact ionization at the n-n/sup +/ junction. The proposed destruction mode has significant similarities with previously described second breakdown at the static breakdown voltage. An approximate analytical model which was derived indicates that avalanche at the n-n/sup +/ junction should become unstable with a time constant on the order of nanoseconds, whereas dynamic avalanche at the p-n junction should be stable. Simulations and measurements show that the reverse recovery safe operating area depends on the n-base width. An approximate equation is proposed to determine the minimum n-base width required for a nondestructive reverse recovery with dynamic avalanche as a function of the reverse peak voltage.

Design and optimization of double-RESURF high-voltage lateral devices for a manufacturable process

Abstract: A simple method for determining the optimal charge balance and processing window of double-reduced surface field (RESURF) lateral devices is presented. The technique is based on the use of simple two test structures that are widely used in ICs, no special test structures are required. The optimal processing window is determined from the bounds over which RESURF is maintainable, and hence, high breakdown voltage is achievable. Using the technique, device designers can set and choose the process conditions of the device's critical layers to yield a manufacturable process prior to actual device layout, and therefore preserves the ability for layout design optimization independent of process optimization. The proposed technique also maximizes the benefits of double-RESURF processing for achieving the lowest on-resistance while maintaining the desired breakdown voltage. Using the technique, the process design and optimization guidelines for a double-RESURF LDMOS built in a high voltage IC technology are discussed and supported with experimental results.

Fabrication and electrical characteristics of polymer-based Schottky diode

Abstract: Metal/polymer Schottky diodes have been fabricated using spin-coated poly(3,4-ethylenedioxythiophene) (PEDT) doped with poly(styrenesulfonate) (PSS) as the p-type semiconductor and aluminum as the metal. The current–voltage and capacitance–voltage characteristics have been studied at room temperature. The breakdown voltage and rectification ratio of the Al/PEDT Schottky diode are about 5.5 V and 1.3×10 4 , respectively. A modified Norde function combined with conventional forward I – V method was used to extract the parameters including barrier height, rectification ratio, ideality factor, as well as the series resistance. This new method allows extraction of device characteristics from measured I – V curve that deviates from ideal I – V curve caused by series resistance.

Growth and scaling of oxide conduction after breakdown

Abstract: Hard breakdown is shown to be a gradual process with the gate current increasing at a predictable rate, exponentially dependent on the instantaneous stress voltage. Adding the hard breakdown evolution time to the standard time to breakdown potentially reduces the projected fail rate of gate dielectrics by orders of magnitude. The scaling of the hard breakdown growth rate with respect to device area, substrate doping, oxide thickness, and channel length are explored. A two-voltage stress procedure is introduced that measures degradation rates on sub-micron devices several orders of magnitude more quickly than a conventional single voltage stress.

Spatial light modulator with charge-pump pixel cell

Abstract: A voltage storage cell circuit includes an access transistor and a storage capacitor, wherein the source of said access transistor is connected to a bitline, the gate of said access transistor is connected to a wordline, and wherein the drain of said access transistor is connected to a first plate of said storage capacitor forming a storage node, and wherein the second plate of said storage capacitor is connected to a pump signal. This arrangement allows for a novel pixel circuit design with area requirements comparable to that of a 1T1C DRAM-like pixel cell, but with the advantage of an output voltage swing of the full range allowed by the breakdown voltage of the pass transistor. A spatial light modulator such as a micromirror array can comprise such a voltage storage cell.

Reduced surface field technique for semiconductor devices

Abstract: A power device and a method for manufacturing the same are provided. The power device comprises a first conductive semiconductor substrate; a second conductive buried layer formed to a certain depth within the semiconductor substrate; a second conductive epitaxial layer formed on the conductive buried layer; a first conductive well formed within the conductive epitaxial layer; a second conductive well formed within the second conductive epitaxial layer, on both sides of the first conductive well; a second conductive drift region formed in predetermined portions on the first and the second conductive well; and a lateral double diffused MOS transistor formed in the second conductive drift region. The breakdown voltage of the power device is controlled according to a distance between the first conductive well and the second conductive buried layer.

Effect of gate-oxide breakdown on RF performance

Abstract: The degradation of S-parameters of 0.16-/spl mu/m nMOS devices due to gate-oxide breakdown is examined. An equivalent circuit model for MOSFETs after gate-oxide breakdown is proposed. The influence of nMOSFET gate-oxide breakdown on the performance of a low-noise amplifier is studied using the equivalent circuit model. Depending on which device and how many fingers break down, the circuit continues to work, despite the fact that the performance of S-parameters and noise figure degrades significantly.

Reduced trapping effects and improved electrical performance in buried-gate 4H-SiC MESFETs

Abstract: Surface effects on the current instability of 4H-SiC MESFETs were studied by comparing different surface structures. The current instability phenomenon was illustrated by bias sweeping methods and current recovery time measurements. A reduction in the current instability was observed for gate-recessed and buried-gate devices compared to the nonrecessed and channel-recessed devices. In addition, the buried-gate devices were found to have higher current density and breakdown voltage compared to the gate-recessed devices, resulting from their shorter effective gate length and lower electric field distribution under the gate, respectively. With high saturation current, high breakdown voltage, and much reduced surface effects, the buried-gate structure is a candidate for high-power SiC MESFETs.

Large area GaN HEMT power devices for power electronic applications: switching and temperature characteristics

Abstract: Large area AlGaN/GaN high electron mobility transistors (HEMT) for power electronic applications have been fabricated. These power devices offer lower on-resistance and higher switching speed than SiC devices due to higher electron mobility and high channel charge density achieved by a heterojunction. The GaN epi-layers were grown on semiinsulating 4H-SiC substrate by metal organic chemical vapor deposition (MOCVD) technique. The device structure was grown on SiC substrates due to its high thermal conductivity. The devices have been optimised with respect to electron mobility, sheet concentration, voltage breakdown, on-resistance and dispersion. Voltage breakdown of 1300 V was achieved on small devices while breakdown in the range 600-900 V was achieved on packaged devices depending on the number of devices that have been paralleled. The power device figure of merit V/sub BR//sup 2//R/sub on/=9.94/spl times/10/sup 8/ [V/sup 2//spl middot//spl Omega//sup -1/ cm/sup -2/], where V/sub BR/ is the breakdown voltage and R/sub on/ is the on-resistance, is the highest among any reported switching devices. Switching losses of large area 600 V/2.5 A power devices were measured using resistive and inductive loading. Switching times of <30 ns were achieved with an on-resistance of 0.4 /spl Omega/ (specific on-resistance=1.7 m/spl Omega//spl middot/cm/sup 2/). The static and dynamic characteristics of GaN HEMT devices were also measured as a function of temperature up to 200/spl deg/C. Finally, the temperature distributions in the active device area were measured using Raman spectroscopy (pyrospectroscopy). This technique can be used to measure temperatures with a spatial resolution of 1-2 /spl mu/m. Device temperatures from both the active areas and SiC substrates have been measured.

Dynamics of pulse phenomena in helium dielectric-barrier atmospheric-pressure glow discharges

Abstract: A study of pulse phenomena in conventional parallel-plate dielectric-barrier controlled atmospheric-pressure glow (DB-APG) discharges in helium is reported. Stable DB-APG discharges are found to occur at arbitrarily low frequencies as long as the gas voltage exceeds the Paschen breakdown voltage, i.e., no lower limit of ∼1 kHz exists for DB-APG operation. The interpulse preionization phenomenon is found to be an artifact of typical ∼10 kHz operation of DB-APG discharges and does not play a role in the formation of a stable pulse. Multiple pulses result from repeated temporally separated breakdown events in the discharge. A relatively simple zero-dimensional model that treats only the Paschen breakdown mechanism in the discharge and charge trapping phenomena at the dielectric surfaces can be used to simulate all important qualitative features of DB-APG phenomena. Finally, we show that control of the pulse intensity, number of pulses in a pulse train, and the time interval between pulse trains can be achiev...

Semiconductor device and method of manufacturing the same

Abstract: A Schottky diode that achieves a predetermined reverse-direction breakdown voltage even if a state of a surface in a vicinity of a Schottky junction interface changes due to a welding of a bonding wire. The semiconductor device having the Schottky junction includes a semiconductor substrate of a first conductivity type. A well region of a second conductivity type is formed in a top surface of the semiconductor substrate. A Schottky electrode is formed on the top surface of the semiconductor substrate. A connecting conductive member is electrically connected to the Schottky electrode. The connecting conductive member is selectively connected to the Schottky electrode above the well region such that a connection surface between the connecting conductive member and the Schottky electrode is not extended above a Schottky junction between the Schottky electrode and the semiconductor substrate of the first conductivity type.

Unpassivated p-GaN/AlGaN/GaN HEMTs with 7.1 W/mm at 10 GHz

Abstract: A novel gate process utilising SiO2 to cover the recess sidewall on the drain side of a p-GaN/AlGaN/GaN high electron mobility transistor is presented Improvements in breakdown voltage and output power are demonstrated with no degradation in small-signal performance

Breakdown probabilities for thin heterostructure avalanche photodiodes

Abstract: The recurrence theory for the breakdown probability in avalanche photodiodes (APDs) is generalized to heterostructure APDs that may have multiple multiplication layers. The generalization addresses layer-boundary effects such as the initial energy of injected carriers as well as the layer-dependent profile of the dead space in the multiplication region. Reducing the width of the multiplication layer serves to both downshift and sharpen the breakdown probability curve as a function of the applied reverse-bias voltage. In structures where the injected carriers have an initial energy that is comparable to the ionization threshold energy, the transition from linear mode to Geiger-mode is more abrupt than in structures in which such initial energy is negligible. The theory is applied to two recently fabricated Al/sub 0.6/Ga/sub 0.4/As-GaAs heterostructure APDs and to other homostructure thin GaAs APDs and the predictions of the breakdown-voltage thresholds are verified.

Electrical properties of HfO2 deposited via atomic layer deposition using Hf(NO3)4 and H2O

Abstract: We report on the electrical properties of HfO2 deposited via atomic layer deposition using Hf(NO3)4 precursor for metal/oxide/semiconductor gate dielectric applications. Thin films, with less than 1% variation in accumulation capacitance over a 150 mm wafer, have been deposited directly on hydrogen-terminated Si wafers. The effective dielectric constant of thin (<10 nm) films was in the range of κeff=10–12, the breakdown voltage was about 6–9 MV/cm, and the leakage current was between 3–6 orders of magnitude lower than that of SiO2. The relative benefit of lower leakage current of HfO2 over SiO2 decreased with decreasing effective thickness. Electron trapping was observed under constant voltage stressing.

Light-emitting diode array

Abstract: PROBLEM TO BE SOLVED: To decrease resistance between mutual electrodes without degrading reverse breakdown voltage of each LED(light-emitting diode), in an LED array in which a plurality of regions of a second conductivity type is arranged on the main surface of a semiconductor wafer of a first conductivity type. SOLUTION: This LED array comprises an active layer (24) of the first conductivity type, inside of which a front face of each second conductivity-type region exists, and cladding layers (23 or 25) of the first conductivity type stacked by sandwiching the active layer (24) have energy gaps larger than that of the active layer (24), and have high impurity concentrations (carrier concentrations).

Semiconductor device with super junction region

Abstract: A semiconductor device includes a first-conductivity-type semiconductor layer which includes a cell region portion and a junction terminating region portion. The junction terminating region portion is a region portion which is positioned in an outer periphery of the cell region portion to maintain a breakdown voltage by extending a depletion layer to attenuate an electric field.

Theoretical and experimental studies for spherical free-conducting particle behavior between nonparallel plane electrodes with AC voltages in air

Abstract: This paper deals with free-conducting particle motion and particle-triggered breakdown in AC electric fields between nonparallel plane electrodes in atmospheric air. Spherical particle motion was investigated theoretically and experimentally under AC voltages with various frequencies, considering the effect of the electrical gradient force and the dependence of the Coulomb force magnitude on the distance between a particle and an electrode. The result shows that when the Coulomb force acting on a bouncing particle changes its direction periodically under AC voltage whose frequency is around commercial power frequency, the electrical gradient force can become effective in initiating particle motion toward decreasing electrode gap regions, causing the particle to trigger breakdown. Moreover, it was found that the direction in which a particle advances horizontally is greatly influenced by microdischarge occurrence when the particle bounces very near to the grounded electrode under high-frequency AC voltage, and that when a particle bounces on an electrode, particle-triggered breakdown voltage is decreased by the effect of microdischarge.

Comparison of the AC barrier corona with DC positive and negative coronas and barrier discharge

Abstract: Results are presented from experimental studies of ac corona discharges between a point electrode and a dielectric-coated plate in nitrogen, argon, helium, and air in the voltage frequency range f=50 Hz–50 kHz. The characteristic features of this type of discharge are compared with the well-known features of dc positive and negative coronas and a barrier discharge between plane electrodes. It is shown that the presence of a dielectric barrier on the plane electrode significantly changes the electric characteristics and spatial structure of the corona, whereas the main phases of the discharge evolution remain unchanged as the voltage increases. With a point electrode, the breakdown voltage of the barrier corona decreases substantially as compared to the breakdown voltage of a barrier discharge with plane electrodes. This leads to softer conditions for the streamer formation in a barrier corona, which becomes more stable against spark generation.

A high performance RF LDMOSFET in thin film SOI technology with step drift profile

Abstract: A radio frequency (RF) LDMOSFET with step drift doping profile on a conventional thin film SOI substrate used for mainstream VLSI technology is evaluated. Detailed simulation indicates that step drift doping can enable increase in the breakdown voltage by as much as 21% in comparison to the conventional uniformly doped drift (UD) LDMOS. In the on-state the kink present in the I–V characteristic of the UD device is eliminated. The other improvements over the UD counterpart include improved on-state breakdown performance, reduced parasitic feedback capacitance, lower on-resistance, improved drain current saturation behaviour and reduced self-heating at bias point.

Decrease of breakdown voltages for micrometer-scale gap electrodes for carbon dioxide near the critical point: Temperature and pressure dependences

Abstract: We performed measurements of breakdown voltages as a function of environmental pressure with 1-μm-gap tungsten electrodes for high-pressure carbon dioxide up to supercritical conditions at different temperatures (305.65, 308.15, and 313.15 K). Breakdown voltage curves exhibit an inflection at around 3 MPa and a drastic decrease near the critical point. The location of the drastic decrease shifts to the high-pressure range and the sharpness and depth decrease with increased temperature. The breakdown voltage in pressure environments higher than that at the inflection point was analyzed systematically using the Townsend theory and density fluctuations. Moreover, comparison with breakdown voltage measurements by 10-μm-gap electrodes indicates that one factor inducing the inflection and the decrease might be electron attachment to existing clusters in dense carbon dioxide.

A numerical study of partial-SOI LDMOSFETs

Abstract: The high-voltage and self-heating behavior of partial-SOI (silicon-on-insulator) LDMOSFETs were studied numerically. Different locations of the silicon window were considered to investigate the electrical and thermal effects. It is found that the potential distribution of the partial-SOI LDMOSFET with the silicon window under the drain is similar to that of standard junction isolation devices. With the silicon window under the source the potential distribution is similar to that of the conventional SOI LDMOSFET. Using the two-dimensional numerical simulator MINIMOS-NT, we confirm that the breakdown voltage of partial-SOI LDMOSFETs with a silicon window under the source is higher than that of partial-SOI LDMOSFET with a silicon window under the drain.

Analysis of surface-state and impact-ionization effects on breakdown characteristics and gate-lag phenomena in narrowly recessed gate GaAs FETs

Abstract: Effects of surface states and recess structures on breakdown characteristics of GaAs MESFETs are studied by two-dimensional (2-D) analysis. It is shown that the breakdown voltage could be raised when moderate densities of surface states are included. However, in a case with relatively high densities of surface states, the breakdown voltage could be drastically lowered when introducing a narrowly recessed gate structure. Effects of impact ionization on gate-lag phenomena in GaAs MESFETs are also studied. It is shown that the gate-lag becomes weaker when including the impact ionization. This is attributed to the fact that the potential profiles along the surface are drastically changed when the surface states capture generated carriers. It is suggested that there is a tradeoff relationship between raising the breakdown voltage and reducing the gate-lag.

Synthesis of zinc oxide varistors with a breakdown voltage of three volts using an intergranular glass phase in the bismuth–boron–oxide system

Abstract: Zinc oxide (ZnO) crystals joined by using an intergranular glass phase were investigated in order to develop surge filters for low-voltage applications and to clarify the current transport mechanism through the junction. The junctions having a ZnO/glass/ZnO sandwich structure were synthesized by using an interfacial glass phase of the Bi–B–O system. A highly nonlinear current–voltage curve was obtained for the ZnO/glass/ZnO junction with Co-doped ZnO single crystals, and the current through the junction at the breakdown voltage was proportional to the 30th power of the bias voltage. Dielectric measurements revealed that a double-sided depletion layer was formed at the interface, and the observed high nonlinearity was ascribed to the corresponding potential barrier formed at the interface.