Showing papers on "Buck–boost converter published in 1968"

Power converter circuits having a high frequency link

Abstract: 1,261,838. Static converters. GENERAL ELECTRIC CO. 9 April, 1969 [16 April, 1968], No. 18197/69. Addition to 1,261,392. Heading H2F. [Also in Division G3] In a power converter as claimed in parent Specification having a control circuit for selectively rendering conductive the solid state switching means in primary and secondary current paths at a switching rate frequency which is high compared with the supply frequency, there is further provided a phase shift circuit coupled to the control circuit to render conductive the primary and secondary current paths at a selected phase angle one with respect to the other, whereby to control the output voltage. The switches may be transistors as shown, Fig. 3, or Gate-turn-off thyristors (Fig. 10, not shown). Converter circuit, Fig. 3.-As in the parent Specification the load voltage e 2 is at the same low. frequency as the input side voltage e 1 , the input current being chopped by transistor switches and applied in opposite directions alternately through a ferrite core transformer 14 at a high frequency switching rate, e.g. 5-10 kHz. The h.f. current at the secondary side is reformed into a low frequency waveform by the secondary side transistor switches also operating at the h.f. rate. Reversibility of power flow through the converter is possible. Each switch means is bidirectional and as shown, Fig. 3, comprises an anti-parallel pair of' transistors Q1-Q2, Q3-Q4, Q5-Q6, Q7-Q8 respectively. Both transistors in a pair preferably receive base current from a control circuit 52 simultaneously and the circuit conditions determine which conducts or alternatively the base signals may be applied via logic circuits. Thus during the positive half cycles of low frequency input, Q2 conducts via diode 29 and in negative half cycles thereof, Q1 conducts via diode 28 and the transformer primary. In normal operation (i.e. 0 degree phase shift between input and output side switches) Q1, Q2 receive base signals at the same time as Q5, Q6 the transistors Q3, Q4, Q7 and Q8 being OFF. During the next h.f. half-cycles Q3, Q4, Q7, Q8 receive base signals and the others are OFF, and so on. D.C. supply.-The connection of the converter to a D.C. source is envisaged wherein the phase shift control is modulated to obtain a desired output waveform to a load. To obtain a sine wave the phase shift is changed between 0 and 180 degrees and then between 180 and 0 degrees according to a sine wave function. Alternatively the output may be D.C. Control circuit, Fig. 9.-An oscillator 58 supplies clock pulses at twice the h.f. switching rate to drive a flip-flop 59 connected to an amplifier 61 which provides base signals for the input side transistors Q1 to Q4. The oscillator pulses are also fed to a phase shifter 62 which actuates a second flip-flop 63 connected to a base signal drive amplifier 64 for the output side transistors. The output drive 63 is thus synchronized with the input drive 59 but is appropriately phase delayed by the shifter 62. Voltage regulation.-The output voltage is sensed by a transformer 48, is rectified and compared in a differential amplifier 68 with a pre-set level VR eg and fed to the phase shifter 62 which causes the output side transistor to change conduction states at a different time from the input side transistors, in either leading or lagging sense. Fig. 4 (not shown) illustrates the output voltage and transformer voltage waveforms for different degrees of phase difference between input and output transistor switches. For 90 degrees phase difference for instance the output voltage is zero. Current regulation.-Load current is sensed by a C.T. 49 and compared with a desired value IR eg in a circuit 71 and a difference value output operates the phase shifter 62 to adjust the output voltage and hence load current. Alternatively the load current signal is compared with a desired current limit value I Lim in circuit 71, the phase shifter operating to reduce the output voltage and current, overriding the voltage regulator. Overcurrent protection.-If overcurrent sensed persists for a time determined by a timer 73 (e.g. 20 low frequency input cycles) a base signal modifying circuit 74 sends a signal to drive amplifiers 61, 64 to cut off base signals to all the transistor switches, or to the input side transistors only, preferably at load current zero to minimize reactive current. Alternatively, circuit. 71 may operate the phase shifter 62 if excess current persists for a pre-set time, to give a full phase shift of 90 degrees between input and output side switching causing zero output voltage. After a time delay to allow reactive current to die all the transistors are turned OFF.

Constant current temperature stabilized signal converter circuit

Abstract: A DIFFERENTIAL AMPLIFIER IS DISCLOSED WHEREIN A CONSTANTCURRENT SOURCE IS PROVIDED WHICH IS REFERRED ONLY TO THE POWER-SUPPLY LEADS. FROM THE CONSTANT-CURRENT SOURCE, BIAS SIGNALS ARE DERIVED WHICH, IN TURN, PROVIDE AD CONTROL CONSTANT-CURRENT SUPPLY MEANS FOR EACH OF THE TWO LEGS OF THE DIFFERENTIAL AMPLIFIER, INDIVIDUALLY. THIS ARRANGEMENT PROVIDES A HIGHLY STABLE, HIGHLY ACCURATE AMPLIFICATION OF INPUT SIGNALS AND MINIMIZES ERRORS DUE TO AMBIENT TEMPERATURE CHANGES.

Digital-analog converter with pneumatic output

Abstract: 1,164,759. Electric digital to pneumatic analogue conversion. SMOLENSKY FILIAL GOSUDARSTVENNOGO NAUCHNO-ISSLEDOVATELSKOGO INSTITUTA TEPLOENERGETICHESKOGO PRIBOROSTROENIA. 22 April, 1968, No. 18894/68. Heading G4P. [Also in Division G3] A digital electric signal is converted to an analogue pneumatic signal by apparatus comprising a number of weights 5 each of which may be applied to a balance lever 1 by energization of the corresponding input 15, the lever being maintained in the balance position by a bellows 6 controlled by nozzle 2 and shutter 3 through pneumatic relay 10. The pressure output 17 is then equivalent to the input code. The weights are calibrated so that their effects are in accordance with their binary scale significance, 1, 2, 4, 8 &c. A sliding bar energized by unit 9 has detents engaging one of two slots in members 13 so that after the input signal has been removed the weights may be retained in the active or inactive position.