Topic
Buffer amplifier
About: Buffer amplifier is a research topic. Over the lifetime, 9526 publications have been published within this topic receiving 63033 citations.
Papers published on a yearly basis
Papers
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TL;DR: In this paper, two new power-saving schemes for high-performance VLSIs with a large-scale memory and many interface signals are described, one is a current-controlled latch sense amplifier that reduces the power dissipation by stopping sense current automatically.
Abstract: Two new power-saving schemes for high-performance VLSIs with a large-scale memory and many interface signals are described. One is a current-controlled latch sense amplifier that reduces the power dissipation by stopping sense current automatically. This sense amplifier reduces power without degrading access time compared with the conventional current-mirror sense amplifier. The other is a static power-saving input buffer (SPSIB) that reduces DC current in interface circuits receiving TTL high input level. The effectiveness of these new circuits is demonstrated with a 512-kb high-speed SRAM. >
290 citations
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07 Aug 2002TL;DR: In this article, a new basic cell for low power and/or lowvoltage operation is identified, which is called flipped voltage follower (FVF) and it is shown that different versions of this cell, called FVF, have been used in the past for different applications.
Abstract: In this paper a new basic cell for low-power and/or low-voltage operation is identified. It is shown that different versions of this cell, called "flipped voltage follower", have been used in the past for different applications. New circuits using this cell are also proposed here.
284 citations
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19 Nov 1982TL;DR: In this paper, a pressure and motion transducer and cooperating circuitry for an implantable medical device is described. But the authors do not specify the type of transducers used.
Abstract: A pressure and motion transducer and cooperating circuitry for an implantable medical device are disclosed. The system includes a pressure transducer 48 and buffer amplifier 40. A clock 70 in pacer 52 periodically energises amplifier 40 via capacitor 62 and lead system 54. The voltage sensed across sensing resistor 74 at node 78 is applied to sample and hold circuit 66 and a continuous pressure signal is provided at output terminal 82.
275 citations
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12 May 1999TL;DR: In this article, a low dropout (LDO) voltage regulator and a system (100) including the same are disclosed, where an error amplifier ( 38) controls the gate voltage of a source follower transistor ( 24 ) in response to the difference between a feedback voltage (V FB ) from the output (V OUT ) and a reference voltage (v this article ).
Abstract: A low drop-out (LDO) voltage regulator ( 10 ) and system ( 100 ) including the same are disclosed. An error amplifier ( 38 ) controls the gate voltage of a source follower transistor ( 24 ) in response to the difference between a feedback voltage (V FB ) from the output (V OUT ) and a reference voltage (V REF ). The source of the source follower transistor ( 24 ) is connected to the gates of an output transistor ( 12 ), which drives the output (V OUT ) from the input voltage (V IN ) in response to the source follower transistor ( 24 ). A current mirror transistor ( 14 ) has its gate also connected to the gate of the output transistor ( 12 ), and mirrors the output current at a much reduced ratio. The mirror current is conducted through network of transistors ( 18, 22 ), and controls the conduction of a first feedback transistor ( 28 ) and a second feedback transistor ( 35 ) which are each connected to the source of the source follower transistor ( 24 ) and in parallel with a weak current source ( 34 ). The response of the first feedback transistor ( 28 ) is slowed by a resistor ( 32 ) and capacitor ( 30 ), while the second feedback transistor ( 35 ) is not delayed. As such, the second feedback transistor ( 35 ) assists transient response, particularly in discharging the gate capacitance of the output transistor ( 12 ), while the first feedback transistor ( 28 ) partially cancels load regulation effects.
210 citations
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20 Jan 1994TL;DR: In this article, a segmented DAC is described in which the outputs of a pair of subword DAC circuits are summed by modulating the offset voltage of a differential buffer amplifier.
Abstract: A segmented DAC is described in which the outputs of a pair of subword DAC circuits are summed by modulating the offset voltage of a differential buffer amplifier. Also described are various alternative DAC embodiments and an operational amplifier input stage in which modulation of the offset voltage of a differential amplifier responsive to a digital signal is accomplished using interpolation techniques for eliminating errors in linearity and monotonicity arising from component inaccuracies.
209 citations