Burst switching

Abstract: Demand for network bandwidth is growing at unprecedented rates, placing growing demands on switching and transmission technologies. Wavelength division multiplexing will soon make it possible to combine hundreds of gigabit channels on a single fiber. This paper presents an architecture for Burst Switching Systems designed to switch data among WDM links, treating each link as a shared resource rather than just a collection of independent channels. The proposed network architecture separates burst level data and control, allowing major simplifications in the data path in order to facilitate all-optical implementations. To handle short data bursts efficiently, the burst level control mechanisms in burst switching systems must keep track of future resource availability when assigning arriving data bursts to channels or storage locations. The resulting Lookahead Resource Management problems raise new issues and require the invention of completely new types of high speed control mechanisms. This paper introduces these problems and describes approaches to burst level resource management that attempt to strike an appropriate balance between high speed operation and efficiency of resource usage.

Abstract: A protocol that supports the sharing of resources that exist in different packet switching networks is presented. The protocol provides for variation in individual network packet sizes, transmission failures, sequencing, flow control, end-to-end error checking, and the creation and destruction of logical process-to-process connections. Some implementation issues are considered, and problems such as internetwork routing, accounting, and timeouts are exposed.

Abstract: The major benefit of a broadband integrated ATM (asynchronous transfer mode) network is flexible and efficient allocation of communications bandwidth for communications services. However, methods are needed for evaluating congestion for integrated traffic. The author suggests evaluating congestion at different levels, namely the packet level, the burst level, and the call level. Congestion is measured by the probabilities of packet blocking, burst blocking, and call blocking. He outlines the methodologies for comparing these blocking probabilities. The author uses the congestion measures for a multilayer bandwidth-allocation algorithm, emulating some function of virtual circuit setup, fast circuit switching, and fast packet switching at these levels. The analysis also sheds insight on traffic engineering issues such as appropriate link load, traffic integration, trunk group and switch sizing, and bandwidth reservation criteria for two bursty services. >

Abstract: A new, high-performance packet-switching architecture, called the Knockout Switch, is proposed. The Knockout Switch uses a fully interconnected switch fabric topology (i.e., each input has a direct path to every output) so that no switch blocking occurs where packets destined for one output interfere with (i.e., block or delay) packets going to different Outputs. It is only at each output of the switch that one encounters the unavoidable congestion caused by multiple packets simultaneously arriving on different inputs all destined for the same output. Taking advantage of the inevitability of lost packets in a packet-switching network, the Knockout Switch uses a novel concentrator design at each output to reduce the number of separate buffers needed to receive simultaneously arriving packets. Following the concentrator, a shared buffer architecture provides complete sharing of all buffer memory at each output and ensures that all packets are placed on the output line on a first-in first-out basis. The Knockout Switch architecture has low latency, and is self-routing and nonblocking. Moreover, its Simple interconnection topology allows for easy modular growth along with minimal disruption and easy repair for any fault. Possible applications include interconnects for multiprocessing systems, high-speed local and metropolitan area networks, and local or toll switches for integrated traffic loads.

Abstract: An architecture for a line card in a network routing device is provided. The line card architecture provides a bi-directional interface between the routing device and a network, both receiving packets from the network and transmitting the packets to the network through one or more connecting ports. In both the receive and transmit path, packets processing and routing in a multi-stage, parallel pipeline that can operate on several packets at the same time to determine each packet's routing destination is provided. Once a routing destination determination is made, the line card architecture provides for each received packet to be modified to contain new routing information and additional header data to facilitate packet transmission through the switching fabric. The line card architecture further provides for the use of bandwidth management techniques in order to buffer and enqueue each packet for transmission through the switching fabric to a corresponding destination port. The transmit path of the line card architecture further incorporates additional features for treatment and replication of multicast packets.