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Showing papers on "Bus network published in 1969"


Patent
John R Andrews1
30 Dec 1969
TL;DR: In this article, a first impedance network connects at one end of the bus in parallel with a termination provided by a master unit, which includes a load impedance for terminating the bus, and a second impedance network complementary to the first, which terminates the bus to ground.
Abstract: In an interconnection bus system, a first impedance network connects at one end of the bus in parallel with a termination provided by a master unit. The termination includes a load impedance for terminating the bus in its characteristic impedance in series with a voltage source for supplying power to the control circuits of a series of devices tapped at different points along the length of the bus. The last device in the series connects to the other end of the bus and includes a second impedance network, complementary to the first, which terminates the bus to ground.

12 citations


Patent
04 Aug 1969
TL;DR: In this paper, a combined display and manual control circuit is connected to the source bus and the destination bus in such a manner that the state of one of the flip-flops can be displayed and manually controlled as selected by an addressing means.
Abstract: In a computer a plurality of flip-flops are connected to a common source bus and to a common destination bus. A combined display and manual control circuit is connected to the source bus and the destination bus in such a manner that the state of one of the flip-flops can be displayed and manually controlled as selected by an addressing means. In particular, means are provided for displaying a selected flip-flop and maintaining the state of that flip-flop, with logical provisions for manually over-riding the existing state and either setting or clearing the selected flip-flop, all with only a pair of leads between the combined circuit and the matrix of flip-flops.

1 citations