Showing papers on "Bus network published in 1972"

Bus transport system for selection information and data

Abstract: A switching unit and a computer system comprising such a switching unit so as to enable processor to converse with a free storage module of a group of processors and storage modules at substantially any given moment. The switching unit comprises a common selection bus for transporting selection information from a processor to a storage module, and a common input and output bus for transporting data between a processor and a storage module. The switching unit furthermore comprises priority circuits so as to deal with simultaneously received requests for the same bus in a given sequence. According to the invention the switching unit comprises registers for storing selection information and/or data, said registers being connected after and eventually also before the relevant common bus.

Data bus transmission line termination circuit

Abstract: A data bus transmission line termination circuit for connection either to the terminal end of a data bus or to an intermediate portion of the bus. The circuit is programmable to either a low-impedance state for connection to the terminal end of the data bus so as to provide an optimum terminating load for the bus, or to a high-impedance state for connection to an intermediate portion of the data bus so as not to load down the latter when so connected. The termination circuit is preferably formed on the same integrated circuit chip as the receiver circuit so as to be located adjacent the effective end of the total transmission line including the portion extending from the data bus proper through the connections and conductors of the board, card, module and chip to the receiver circuit on the chip.

Bus system for interconnecting systems of a communication switching system

Abstract: A bus system arranged such that the number of interconnection points between subsystems or modules are substantially reduced so that interfacing costs likewise are reduced. The multiple for continuing the bus is located on an interface connector assembly which provides an interfacing between the bus cable and the subsystem or module, so that the continuity of the bus can be maintained, regardless of the system status of any subsystem or subsystems. Normally, with other similar bus systems, the continuity of the bus is disrupted if a subsystem is taken out of service. Furthermore, unlike many other bus systems, the bus can be extended in vertical and/or horizontal directions. The bus system also is such that the bus can be easily terminated by simply inserting a terminator card on the interface connector assembly, or it can be extended by withdrawing the terminator card and plugging in a bus jumper cable with a terminator card at the last module.

Loop type data highway system for data transmission

Abstract: A loop type data highway system for data transmission in which a plurality of stations each including at least a series connection of a receiver, control gates and a transmitter are connected in series with one another by a single common bus to form a closed loop. Each of those stations comprises means for applying a request for occupying the common bus, means for confirming as to whether the common bus is idle and available, means for turning off the control gates thereby opening the loop after confirmation of the fact that the common bus is idle and available, means for delivering a priority code A peculiar to the specific station to the common bus through the transmitter, and means for comparing the priority code A with another priority code B received by the specific station for the purpose of determining the priority order. The specific station determines that it succeeds in occupying the common bus when A = B and fails to occupy the common bus when A NOTEQUAL B. The specific station determines that another station having a lower priority order than the specific station applies a request for occupying the common bus simultanaeously with the request from the specific station when A > B, and that another station having a higher priority order than the specific station applies a request for occupying the common bus simultaneously with the request from the specific station when A < B.

Priority network for devices coupled by a multi-line bus

Abstract: A priority network including a multiple line bus coupled with a plurality of priority seeking devices, the device furthest down the bus having the lowest priority. In other words, the priority of each device is dependent upon its proximity to the input end of the bus. Each device determines whether it has priority or not by looking back at the priority indications of two or more previous devices coupled with the bus thereby decreasing the time required for a given device to gain access with a processor coupled with the bus. Means are also provided for clearing the priority indications of each of the plurality of devices, once a device has gained access with the bus and processor, thereby increasing the speed for clearing the priority network.

Improved bus system for interconnecting subsystems of a communication switching system

Abstract: A bus system arranged such that the number of interconnection points between subsystems or modules are substantially reduced so that interfacing costs likewise are reduced. The multiple for continuing the bus is located on an interface connector card which provides an interfacing between the bus cable and the subsystem or module, so that the continuity of the bus can be maintained, regardless of the system status of any subsystem or subsystems. Normally, with other similar bus systems, the continuity of the bus is disrupted if a subsystem is taken out of service. Furthermore, unlike many other bus systems, the bus can be extended in vertical and/or horizontal directions. The bus system also is such that the bus can be easily terminated by simply inserting a terminator card on the interface connector card, or it can be extended by withdrawing the terminator card and plugging in a bus jumper cable with a terminator card at the last module.

Sequential addressing network testing system

Abstract: The testing apparatus disclosed herein is adapted to test backplane wiring so as to determine if all desired connections exist and whether any undesired connections may be present. Such backplanes typically comprise a multiplicity of terminal points which may be interconnected in arbitrary manner to form a plurality of networks of connected points. The tester employs an addressable switching and memory unit for each terminal point. When addressed, each point is first connected to a first bus and, when the addressing is terminated, is thereafter connected to a second bus, this second connection being maintained under the control of the memory or latch associated with each switching unit. Prior to being addressed, each point is in effect isolated by the switching unit and allowed to float in potential. As the successive points in a given network are addressed, the system tests for continuity between the first and second buses to determine if the desired connections exist. After all terminal points which should be in the selected network have been latched into connection with the second bus, all remaining points are commonly switched into connection with the first bus. Testing for isolation at this time determines whether any undesired connections affecting the selected network are present.

Bus control arrangement for a communication switching system

Abstract: The system has duplicate central processors, each having its own bus. Subsystem modules include program memory, data base memory, status detector, register-senders, markers, etc., each having one or more memory word stores. Bus interface units of identical construction are interposed between the subsystem modules and the busses. Some modules such as program memory are duplicated and each connected to one bus, while others are connected via their interface unit to both buses. All memory addresses are accessed from a processor via its bus, each address being effective to select only one interface unit, and the complete address being then passed to the subsystem module to read or write a data word. The bus comprises control conductors, and data conductors for both address and data in either direction. A bus control unit at the central processor provides an address cycle followed by a data cycle indicated by signals on the control conductors.

Loadflow computer and dc circuit modules employed therein for simulating ac electric power networks

Abstract: A hybrid loadflow computer arrangement includes a modularized analog network simulator and a digital computer which acquires and processes on-line data and operator data related to the power system for which a loadflow problem is being solved. The analog simulator includes modular circuits representative of power system busses and lines and the interface between the digital computer and the analog network simulator is provided by analog-to-digital and digital-to-analog converters and by line outage contact closure outputs. The hybrid arrangement operates iteratively, with the analog network simulator providing a bus voltage solution for a set of network simultaneous equations and the digital computer providing bus load and generation injection current calculations and convergence steering control. The modular bus and line circuits are interconnected to simulate the power system and operate stably in forcing currents and voltages to satisfy current and voltage laws to provide the bus voltage solution. Integrated circuit operational amplifiers are employed as error current integrators in bus modules and as voltage difference amplifiers in line modules.

Call concentrator switching matrix

Abstract: A substantial reduction in blocking is achieved in a call concentrator, while increasing the number of subscribers served and reducing the number of trunks and relays required, as compared to prior art devices, by providing a linking bus network interposed between the subscriber lines and the trunks, and using separate line relay and trunk relay matrices to interconnect the lines and trunks with the linking bus network. Substantial reductions in cost of installations serving less than the maximum number of lines are effected by placing all matrix components on plug-in printed circuit boards so that the smaller installations may be served by partially equipped matrices, and growth easily accommodated without service interruption. The costs of providing reliable power for the matrix are reduced through the use of magnetically latched relays in the matrix.