Showing papers on "Bus network published in 1977"

Process control system with local microprocessor control means

Abstract: In a computer control system a central processor unit (CPU) is provided as a primary control center. A data bus interface controller is connected to interface between the CPU and a serial data communication bus. The interface control unit controls the traffic on the data bus as well as interfacing the format between serial data on the data bus and the parallel data receivable by the CPU. A plurality of process interface units are connected to the serial data bus. Each of these process interface units (PIU) has a plurality of process input/output devices connected thereto and controlled thereby. The PIU's exercise a significant amount of control capability including having an internal microprocessor unit. By performing many of the functions heretofore provided by the central processor unit, the PIU significantly reduces the amount of data which must be transmitted via the serial data bus to the CPU. By requiring the data bus only for reporting of change signals, or data requested by the CPU, further economies in the use of the data bus are effected. By thus reducing the amount of data that must be transmitted on the data bus, more efficient use is made of both the CPU and the communication bus. The PIU includes facilities for scanning all of the input/output devices associated therewith; manipulating the gathered data to perform such operations as offset correction, gain optimization, linearization where needed, sequence of events tabulation, reasonableness testing, digital smoothing, process limit testing, normalization, scan frequency controlling and cold junction compensation where needed; the storing of the results in local memory for transmission to the CPU through the bus interface control unit. It has the capacity to request access to the communication bus when required. When access to the bus is acquired by the CPU, gathered data may be transmitted in block form or on a word-by-word basis as required.

A mathematical programming algorithm for optimal bus frequencies

Abstract: Assume that a bus network is given, i.e. we are given a network of streets on which certain bus lines have been set up. Let the total number of buses be given. Assume furthermore that the total dem ...

Routing and control in a centrally directed network

Abstract: TYMNET I is a centrally directed network with over 200 nodes interconnected in a topology that allows alternate paths between nodes in the network. Routing within the network is done by a central supervisor program, with full knowledge of network topology and network load. Within network nodes routing is table driven.The supervisor communicates with nodes through a command tree that is built at network takeover time. The supervisor has no a priori knowledge of the network topology when it starts network takeover, and the topology may change while the supervisor is in control. The control tree is dynamically modified by the supervisor to accommodate the new topology.

Computer system comprising at least two individual computers and at least one system bus bar

Abstract: A computer system comprises at least two individual computers and at least one system bus bar which is composed of a system data bus and a system address bus. In each case, between one of the individual computers and the system bus bar there is arranged a traffic memory which is designed for optional access from the system bus bar or from the individual computer. The system bus bar has n (where n=2, 3 . . .) system data buses for word-parallel traffic of n data words, and each traffic memory is designed for optional word-parallel access in n-times word width from the system data buses or word-sequential access in single word width from the individual computer or from one of the system data buses.

Common-bus occupying system

Abstract: PURPOSE: To reduce the number of signal lines by providing signal lines between a bus controller and each central processor only for request-to-use and permit-to-use signals and by using the common bus for control information requiring several signal lines within allotted time. CONSTITUTION: To one commun bus 11, several central processors 12-0 to 12-3 and main storage unit 13 are connected, and bus 11 and common bus controller 14 are connected together via one bundle of signal lines 21. In addition, respecitve processors 12-0, 12-2 and 12-3, and controller 14 are connected together via request- to-use lines 15-0 to 15-3, and permit-to-use lines 17-0 to 17-3 respectively. In this way although request-to-use lines and permit-to-use lines are provided between respective processors 12-0 to 12-3, and controller 14 only for request-to-use signals and permit-to-use signals, control information signals are transferred by using bundle of signal lines 21 provided between bus 11 and controller 14 according to a clock interval. COPYRIGHT: (C)1979,JPO&Japio

System bus module for a controller

Abstract: In a control module having a central processor coupled through a system bus including data, address and control lines to access a data memory, a direct access apparatus is included coupled through the system bus to request a hold of the central processor and upon acknowledgement for directly accessing the data memory through the system bus for directing the control registers of a host machine. Also included are a diriment element interfaced to the central processor for receipt of control signals on the system bus from the direct access apparatus for hold request and for transmission of first and second control signals on the system bus from the central processor for acknowledgement, and a timed protocol unit for supervising the data, address and control signals transported on the system bus. The timed protocol unit comprises an address control coupled through the system bus to the central processor for disenabling address signals upon receipt of the first acknowledgement signal on the system bus from the diriment element, and a data control coupled through the system bus to the central processor for bidirectionally disenabling data signals upon receipt of the second acknowledge signal on the system bus from the diriment element.

Decomposition approach to bus network design

Abstract: This paper presents a decomposition approach to bus network design in which the task of network design is accomplished through the optimization of a series of subproblems. Bus routes are classified into several types, each having a different development priority. The basis design unit in the proposed approach is a development stage. Only one type of bus route is to be considered in each stage. After the number of bus routes to be included in each stage is determined, the origins and destinations of potential routes are identified. Optimal alignment connecting each pair or origin and destination is subsequently located.

Bus connection detector circuit for bus connection matrix circuit

Abstract: A bus connection detector circuit used for a switching network comprising a plurality of semiconductor switch elements of PNPN semiconductor four-layered structure, which are arranged in a matrix array and adapted to conduct upon the application of a potential thereacross. A plurality of diodes are connected at their one end to horizontal and vertical buses, respectively, and connected at their other end in common to one end of a voltage regulating diode for detection of the potential of the buses, and the other end of the voltage regulating diode is connected to a voltage level sensor, thus making up a single bus connection detector circuit, so that the connection of each bus can be detected by the single bus connection detector circuit.

Bus control system of composite computer system

Abstract: PURPOSE: To improve the efficiency in use of a high-speed bus when a master device requests a slave device in another system to send data, by enabling the master device to release the high-speed bus after sending out an address and to transfer the data to the requesting device at the time in point when the answer of the data arrives. COPYRIGHT: (C)1979,JPO&Japio

Local device in a control information transfer system

Abstract: In a control information transfer system in which a central device and a plurality of local devices are respectively interconnected through a control information bus, the local devices are designed to be used in common to the case of the control information bus having the configuration of serial connection suitable for a small system and the case of the control information bus having the configuration of parallel connection suitable for a large system. This is realized by the addition of a very small amount of hardware.

Bus line chekcing device

Abstract: PURPOSE: To ensure an error detection in a bit correspondence both for the device control bus and the date bus, by including the set signal to be given to the output bus line register and the reading signal which is used to put the output bus line register onto the input bus line into the matrix circuit COPYRIGHT: (C)1979,JPO&Japio