Showing papers on "Bus network published in 1979"

Processing system with dual buses

Abstract: A processing system is disclosed in which transfers between processors and memory are made on dual redundant buses. In a transfer, the transmitting unit sends the same information simultaneously on each of the buses. The receiving unit makes parity checks on each bus, and compares the information received on one bus with that received on the other bus. The receiving unit includes means for implementing a decision rule, based on these checks and comparison, to choose from which bus to take information, if either.

Digital bus communications system

Abstract: A time division multiple access communications system includes a plurality of terminals coupled to a common signal path, or bus. In one form of the invention, time slots are allocated on a relatively static basis to various requesting terminals to establish communication links over the bus. Control of bus access and communication link formation is distributed over the entire system, wherein at least one terminal having the slot allocation capability may address selected other terminals and allocate the capability among those other terminals. In a second form, subscriber terminals contend for access to the bus. In a third form, a dual mode communication system is provided incorporating both the allocation and contention modes of operation.

Bus collision avoidance system for distributed network data processing communications system

Abstract: A transmission collision avoidance scheme for a distributed network data processing communication system including a half-duplex communication board coupled to the system bus (3). In addition to a serial data bus (120) and a clock bus (121), the system bus is configured to include a busy status line (122) that is monitored by each device connected in the system. When a device desires to send a message, it initially proceeds to busy out the busy status line, by causing a busy flag (97) to be placed on the line. It also checks the busy status line (83) in order to ascertain whether a busy nag was already set namely, whether another device has already requested service. If the bus is busy, the device cannot transmit until the bus becomes free and the requesting device resets the bus busy flag for a retry interval. Assuming that the bus is free, the transmitting device (22) proceeds to transmit. When the device for whom the message is intended receives the message, it sends an acknowledgement message back to the transmitting device, signifying a successful transmission. Because of circuit operation and propagation delays, there exists the possibility of more than one device setting a busy nag and checking the status of the bus without being aware that another device is simultaneously requesting use of the bus. In this event, a transmission collision will occur, so that the intended receivers see no sensible transmission and, consequently, return no acknowledgement messages to the collision-participating transmitters. When a transmitter fails to receive an acknowledgement message, it assumes that a collision has occured, and proceeds to repeat the above procedure for transmitting its message pursuant to a prescribed priority scheme, the higher priority device being assured of transmitting its message without a collision on the bus with a message from the lower priority device.

Intelligent main store for data processing systems

Abstract: A data processing system comprising an active and intelligent main store including a main memory, a main store controller for accessing the main memory in a manner allowing different address and data structures, and a main store bus connected to the controller. At least one processor of a first type is connected to the main store bus, this being an auxiliary processor for performing input-output and other operations. At least one processor of a second type also is connected to the main store bus, this being an execution processor for fetching, decoding and executing instructions. All or some of either or both of the auxiliary processors and execution processors may be different. A supervisory processor for initiating configuring and monitoring the system is connected to the main store bus. A communication bus is connected to the processors of the first and second types and to the supervisory processor. A diagnostic bus connects the supervisory processor to each of the processors of the first and second types. An input-output bus ensemble is connected to the supervisory processor and to each auxiliary processor. At least one device and associated device controller can be connected to the input-output bus ensemble. At least one direct memory access controller can be connected between the main store bus and the input-output bus ensemble.

Port logic for a communication bus system

Abstract: Apparatus and method for enabling asynchronous, collision-free communication between ports on a local shared bus network which is efficient in the use of bus bandwidth and which, in one embodiment, provides a bounded, guaranteed time to transmission for each port.

Distributed first-come first-served bus allocation apparatus

Abstract: First-come, first-served bus allocation apparatus (110, 120, 140, 141, 142) are distributed to each device sharing a common resource, such as a data bus. Bus allocation is achieved by placing each request from a device for control of the resource in an ordinal ranking with respect to requests from other devices. Requests are assigned positions in the ordinal ranking concurrent with other activity on the data bus. Substantially simultaneous requests are ordered sequentially. As control of the data bus is relinquished by one device, control is transferred to the device whose position in the ordinal ranking is contiguous with that of the relinquishing device. Delay in making this transfer is substantially eliminated.

Computer system with two busses

Abstract: A computer system having two busses which are shared by one or more processors, one or more memories, one or more input/output channels and a bus control mechanism. One of the busses is used for the transmission of original messages from the processors and/or I/O channels to the memories or the bus control mechanism. The other bus is used for the transmission of reply messages by the memories or the bus control mechanism to the senders of original messages requiring a reply. The bus control mechanism includes a first control means for controlling priority and usage of the first bus and a second control means, independent of the first control means, for controlling reply message traffic over the second bus. The reply message control means is arranged to handle reply message traffic on a priority basis and a time availability basis so as to prevent hang up of the reply message bus.

Execution unit for data processor using segmented bus structure

Abstract: A data processor having a novel execution unit (16) is disclosed which employs a segmented bus structure (10, 20, 32; 12, 22, 34) and a dual port register cell (138) in order to increase circuit density and in orderto allow address and data computations to occur simultaneously. The disclosed circuit is designed to interface with an external 16-bit bidirectional data bus and an external address bus having as many as 32 address bits.

Bus allocation synchronization system

Abstract: An improved bus allocation system to control a time division multiplexed digital data bus used by a plurality of signal sources such as a number of digital processing components in a decentralized system in which there is no single entity controlling the bus. The system includes a mechanism for maintaining allocation synchronization under realistic, non-ideal conditions in which noise or other error producing interferences may be present. Each signal source is provided with a bus interface unit having an address counter which operates in conjunction with an allocation vector. The counters operate through a repeating cycle of counts and one or more of the counts in each cycle based on its allocation vector. Each address counter is synchronized during or following the receipt of a message using a unique comparison sequence of comparisons. By means of this system the value of all counters within the range of synchronization are made identical in response to a bus allocation synchronization signal. If a given address counter is off too many counts to be synchronized, the transmitter of the associated device is disabled until it can be re-synchronized by a later synchronization signal. Thus any device having a counter that is out of synchronization for any reason cannot transmit until such synchronization is restored. This prevents interference occasioned by more than one device using the bus at a given time.

Controller for data processing system

Abstract: A controller for at least one secondary storage device for use in a data processing system having a system bus which accommodates a device or a CPU that first acquires control, a device bus that has the same address, data and control format as the system bus and a cache bus which maintains its own timing for address and data signals. The controller has means for transferring the control signals between the device bus and the system bus to establish control over the system bus by the secondary storage device. The data, address and control signals are transferred between the device bus and the cache bus in accordance with the cache bus timing.

Priority system with low speed request bus

Abstract: A new polling apparatus for units on a shared bus of a data processing system operates with a relatively slow multi signal line request bus and a relatively slow local counter. The local counter divides each time slot into a few sub-slots. Each sub-slot is assigned to two or more units in a priority sequence and during a sub-slot the assigned units contend for access to the bus by raising signals on particular lines of the request bus according to their priority within the sub-slot.

Data processing system incorporating arbiters and selectors to allocate transmissions by multiple devices on a bus

Abstract: Disclosed is a data processing system which includes a plurality of devices that communicate in a time-shared fashion over a single data bus. The system also includes a network of arbiters and a network of selectors. These networks interconnect the plurality of devices, and they operate to insure that only one device transmits on the bus at a time. The networks are asynchronous and modular in design.

Bus priority control method in loop bus network system

Abstract: In a loop bus network system where a plurality of processors are connected to a unidirectional loop bus and each of the processors generates a transmission message with a level number which designates the bus use priority of the message, each of node processors, in which message transmission request is generated, transmits to the loop bus a bus control data including a level number of the message generated therewithin and a data which represents the bus use priority assigned to each node processor for that level number Each of the node processors compares the bus control data transmitted therefrom to a succeeding node with a control data received from a preceding node and then transmits only the larger data of the compared two data, thereby to ascertain that only one bus control data propagates around the loop and a loop bus use priority is assigned to one of the node processors that has generated the above-mentioned one bus control data

Optically coupled serial communication bus

Abstract: A master slave controller communication system is disclosed wherein intercommunication occurs between a master controller and a slave controller over the same communication control line. The communication control line contains three busses. At least one bus is a forward/reverse bus and a second bus is a power bus.

Connection system for plural data processors

Abstract: PURPOSE: To enable the data transmission efficiently with minimum number of common bus signal lines, by performing the data transmission between the processing units in multiple branch connection with T-branch wired-OR system to the common bus consisting of a pair of signal lines. CONSTITUTION: The processors 3 1 ...3N including microcomputer is in branch connection with T-branch wired-OR system to the common bus 1 via the bus interfaces 2 1 ...2N. Further, the failure monitor and detecting processor 5 to monitor and detect the abnormity or failure produced in the interfaces 2 1 ...2N corresponding to the units 3 1 ...3N or the units themselves, is connected to the bus 1 via the bus interface 4. If either one of the units 3 1 ...3N has failute, the units 3 1 ...3N are locked and lock release command is individually delivered. Further, the unit without response is regarded as failed unit. Thus, the common bus signal lines with minimized number can perform the data transmission efficiently. COPYRIGHT: (C)1981,JPO&Japio

Circuit arrangement for time division multiplex data transmission with a bus system

Abstract: An arrangement is disclosed for time division multiplex data transmission with a bus system which includes a bus line and a plurality of participators or terminals connected to the bus line in data transmitting connection with each other in a predetermined succession in a predetermined combination, in which each participator or terminal has at least one programmable counter having a counting input for connection with a synchronizing signal generator and an output for connection with a switching device to produce a data transmitting connection between the bus line and a data source or sink of this participator or terminal, whereby the counters of all participators or terminals are synchronized with each other. The arrangement includes apparatus to detect short circuits and to shut down individual sections of the bus line to protect the individual sections without shutting down all sections.

Control of service reliability in transit networks

Abstract: Service reliability is important to both the transit user and the transit operator. This report represents the initial phase of a study of various strategies for control of service reliability in transit networks. Specifically, this report focuses on: (1) identification of possible control strategies; (2) development of a bus network simulation model to enable testing of alternative strategies; (3) analysis of the relationship between passenger wait times and service reliability; (4) tests of the effects of network structure on reliability; and (5) preliminary tests of a limited set of control strategies. Major conclusions are: (1) passenger wait time is very sensitive to service reliability; (2) new insights have been gained into the causes of vehicle "bunching" along routes; and (3) a number of potentially useful control strategies have been identified.

Data highway transmission unit

Abstract: PURPOSE:To enable the data transmission with high reliability with a simple circuit constitution, by connecting both end points with the bus control unit provided at both end points of the information bus provided in ring shape at open wire of the information bus. CONSTITUTION:At normal state without open wire, the bus control unit 11 opens both end points A, B of the information bus 1 to form one bidirectional common transmission line taking the A, B as the end points. Next, if open wire is caused at the part X of the information bus 1, the bus control unit 11 connects the A, B of the information bus 1 to form one straight line bidirectional common transmission line taking the failed point X as both end points. Accordingly, since one straight line bidirectional common transmission line accessible from the entire data station 2b can be formed both for normal and failed modes, the mutual communication between arbitrary data stations can be made.

Interprocessor control system

Abstract: PURPOSE: To make it possible to apply a general-purpose microcomputer to duplexed redundancy constitution, by exercising access control between processors via both common buses by coupling common buses of two processing systems by a control circuit. CONSTITUTION: Common bus 14 to which processor 11, memory 12 and channel system device 19 to be controlled constituting the 1st microcomputer are connected respectively and common bus 24 to which processor 21, memory 22 and channel system device 29 to be controlled are connected respectively are coupled together by bus coupling control circuit 30. Further, processors 11 and 21 are connected directly to bus coupling control circuit 30 via control lines 31 and 32. Only one processor, when in operation, is permitted to occupy both the common buses, and both the processors, when in operation, are so controlled that both the common buses are selected on priority basis of disconnected. COPYRIGHT: (C)1981,JPO&Japio

Multiplexing system for a solid state timing device

Abstract: A CMOS timing device having a primary oscillatory reference source, a chain of series connected bistable divider stages whose data outputs are applied to a decoder/display by way of a multiplexing network. The multiplexing network is comprised of a plurality of multiplex sections, each section having a plurality of data transmission channels or paths. Each channel includes a plurality of MOS devices of a first type connected to a common bus. All channels driving the common bus share a single MOS device of a second type which provides a complementary function with respect to the first type to establish predetermined operating voltage levels for the data logic states carried by the common bus. The data on the common bus of each multiplex section is stored in a CMOS bistable latching type flip-flop whose regenerative feedback path is MOS device controlled.

Bus control device of multiprocessor system

Abstract: PURPOSE: To make it possible that respective processors occupy a bus equally, by controlling variably the priority of bus requests in the bus control device, in the system where plural processors share devices with the common bus. CONSTITUTION: Bus request signals REQ 1 WREQn from plural processors (PC) are input to priority encoder 7 through gate circuits 121W12n for the request mask of the bus control device. Binary output signals B 1 WBm of encoder 7 are input to zero detecting circuit 10 and decoder 8. When contents of signals B 1 WBm are zero, circuit 10 sets request mask FFs 111W11n and opens circuits 121W12n. When signals REQ 1 WREQn are simultaneously generated, the priority is selected by encoder 7, and signal A 1 is output in decoder 8, and the FF for bus permission is set, and not only bus permission signal ACK 1 is generated but also FF111 is reset and circuit 121 is closed. Thus, even when REQ 1 is generated again after the completion of REQ 1 , the precedence of the preceding request is taken if another request signal is generated. COPYRIGHT: (C)1981,JPO&Japio

A Microprocessor-Based Multi-loop Network System

Abstract: A microprocessor-based multi-loop network system (MLNET) has been developed. MLNET has been designed to be a flexible and reliable low cost local network suitable for small systems. MLNET consists of many nodes and a number of communication loops, whose control is distributed all over the nodes to increase its reliability. This paper describes MLNET, emphasizing on details of its network topology, intra-loop transmission and inter-loop communication schemes, and its hardware and software.

Equilibration of supply and demand in designing bus routes for small urban areas

Abstract: A methodology that models the interactive relations between bus-system supply and demand and results in an optimal or near-optimal bus-route structure is described. On the supply side, the route structure is developed by using a heuristic algorithm called SWEEP, written in FORTRAN language. The algorithm partitions the total bus stops in the urban area into sectors and uses a three-optimum traveling-salesman algorithm or Hamiltonian-path algorithm to link these stops. The objective function of the algorithm is to minimize the total distance traveled by all buses, subject to the capacity and distance constraints on each bus. On the demand side, the program uses the already developed bus network to determine the percentage of total community travel that requires bus service. This is carried out by using a disaggregate mode-choice model that is based on the total time and cost difference between travel by automobile and travel by bus for each individual user. costs of bus operations are calculated from a four-variable unit-cost model. An iterative, interactive feedback process is used to achieve the equilibrium state of the transportation market. Equilibrium is reached when the bus share of the transportation market cannot be increased by improving the bus network, under certain resource conditions and financial constraints. The program is tested in developing feeder bus routes to the proposed Glebe Metro station in Arlington County, Virginia. (Author)