Showing papers on "Bus network published in 1980"

Digital data communication system

Abstract: A digital data communication system including a data source and a source interface, a digital data bus, for transferring encoded information from the data source to one or more receivers, each having a receiver interface. The source interface is adaptable for controlling the rise and fall times of the signals on the bus at a plurality of frequencies. It is directly coupled to the bus and terminates the bus in its characteristic impedance. The receiver interface operates at a plurality of frequencies and is directly coupled to the bus.

Bus interface units sharing a common bus using distributed control for allocation of the bus

Abstract: A distributed data processing system is disclosed which has truly distributed control. A plurality of bus interface units (BIU) are interconnected by the distributed system data bus (DSDB) which includes a clock line, a serial command line (CMD), a serial bus allocation line (BAL) and a two byte wide data bus. A central clock connected to the clock line which defines the message frame timing, is the only centralized "control" element in the system. Each BIU may in turn be connected to either one or several data processing units, an I/O port, or a bridge connecting to still another similar bus network.

Distributed bus arbitration method and apparatus

Abstract: A bus interconnects a plurality of elements to form a distributed signal processing system When two or more elements attempt to use the bus simultaneously, a method of arbitration occurs whereby each element places its element arbitration code on assigned lines of the bus forming a composite complementary code Arbitration apparatus in each element determines an element's priority relative to other elements based on said composite complementary code The lower priority elements drop off the bus until only the highest priority is left whereupon it uses the bus to transmit its block of data The distributed aribration apparatus has special advantage in a fault-tolerant system where it is critical that single point failures do not cause the complete system to f

Masterless and contentionless computer network

Abstract: A computer network is disclosed in which a plurality of computer stations are interconnected by a single bus and wherein access to the bus is controlled by the computer stations themselves through an adapter unit at each station. Each adapter unit is assigned a unique number. When the network is running normally, control of the bus is continually passed from one live adapter unit to another in numerical sequence and the bus is active with messages, control signals or status signals from the particular adapter unit that happens to be in control at the time. If, for any reason, there should be no activity on the bus for a preselected time interval, all adapter units detecting this condition enter an election mode to elect from amongst themselves one adapter unit to assume control and resume activity. In the election mode, each participating adapter unit sends a pulse out over the bus and then monitors the bus for activity for a time period directly proportional to its assigned number. The first adapter unit whose time period expires without detecting activity is the winner and sends another pulse out over the bus causing the other participating adapter units to detect activity before their time periods expire and thus become losers in the election. Each adapter unit includes a line activity indicator for monitoring the bus for activity, a timer for measuring time, a switch which is used in generate pulses and circuitry for interfacing the computer at its associated station to the bus.

A supply model for public transit services

Abstract: Assume that a bus network is given, i.e. we are given a network of streets on which certain bus lines have been set up. Let the total number of buses be given. Assume furthermore that the total demand for bus transportation is given in the form of the marginal totals of an origin-destination matrix, i.e. the total demand for travel from certain origins as well as the total demand for travel to certain destinations is given. Problem: Determine the complete travel pattern and decide which bus frequencies to use on the various lines. The problem is formulated as a non-linear programming problem in the form of a compound minimization problem. The most interesting features are that the model explicitly takes into account capacity constraints on the buses, and that the distribution of trips between different zone is influenced by the frequencies of the bus lines. An iterative algorithm to solve this problem is developed. The algorithm converges to stationary points. This scheme employs as a component an algorithm for the combined distribution- assignment problem in traffic planning which is developed by using decomposition. The model has been tested on the bus network in the town of Linkoping (80,000 inhabitants). The model suggests certain actions which are in agreement with the actions actually taken by the bus operator.

Data processing system having multiple buses

Abstract: A data processing system having a bus system for data communication employs a bus splitting circuit. This bus splitting circuit permits selective connection and isolation of individual buses of the bus system. A more flexible assortment of data communications paths among logic blocks coupled to the bus system is permitted by this arrangement in which some logic blocks may be coupled during one state of the bus splitting circuit and decoupled during the other state of the bus splitting circuit. By separating some of the buses via the bus splitting circuit, dual data transfers using the split buses is possible. In a preferred embodiment at least one of the logic blocks is a memory which is coupled to more than one of the buses, thus permitting simultaneous read and write operations, dual read operations or dual write operations.

Method and apparatus of bus arbitration using comparison of composite signals with device signals to determine device priority

Abstract: A bus arbitration method and apparatus for determining which of a plurality of devices desiring access to a common bus will gain access to the bus when it becomes available. Using the change of state of a common BUSY line to synchronize the simultaneous initiation of the arbitration process in each competing device, each device outputs a unique signal to a common arbitration line or lines. Each device monitors the composite signal on the arbitration line or lines and determines its priority relative to other devices. The device with the highest priority gains access to the bus and outputs a signal to the BUSY line until the bus is available for another arbitration.

Serial communications bus for remote terminals

Abstract: A communication system is provided for use in an electronic accounting system. The system includes a plurality of remote terminals for data entry, a serial data bus, a universal synchronous/asynchronous receiver/transmitter (USART), a priority interrupt controller and a processor connected to the bus to allow processor controlled bidirectional communication over the bus.

Single transmission bus data network employing a daisy-chained bus data assignment control line which can bypass non-operating stations

Abstract: This disclosure relates to a network of stations having a single transmission bus. A bus assignment control line is daisy-chained to all of the stations to form a closed loop such that an assignment signal will circulate through the loop and return to the originating station after each station has been given an equal chance to be serviced. Each station is provided with means to detect when the preceding station is malfunctioning or is not turned on, and in response thereto, to transmit a bus assignment control signal to the next succeeding station if it itself does not require access to the transmission bus.

Method of attaining communication of data packets on a local shared bus network and local shared bus network

Abstract: Asynchronous, collision-free communication of data packets is provided on a local shared bus network interconnecting a plurality of N ordered transceiving ports (1,2,3....,J,...N). The bus network includes a data bus (20) having a propagation delay time T and a control line (26) having a propagation delay from port J to port N of R(J), each port J including means (40) for ascertaining the presence of a data packet on said data bus at said port J, and being adapted to send and receive on said data bus variable length data packets. Each port J upon having a packet available for transmission executes the steps of placing a signal S(J) on said control line (26) to communicate to ports J + 1, J +2,...,N an intention to transmit a packet, delaying transmission for the time interval R(J) + T, ascertaining that no signal indicating an intention to transmit is being received at port J from any of ports 1,2,...,J- 1 , and that said data bus (20) at port J is unoccupied, transmitting the packet and terminating signal S(J). Prior to placing the signal S(J) on the control line (26), the port J ascertains that the data bus (20) is unoccupied for a time period 2T.

System for controlling access to a common bus in a computer system

Abstract: Circuitry for affording access to a common passive bus by a plurality of computer devices connected to the bus. Each of the devices is provided with the circuitry, which operates in three sequential phases: a bus request phase, an address phase and a data transfer phase. Circuitry interconnecting the bus connections for permitting a device to initiate the bus request phase only if all devices superior to it are not in the bus request phase thereby establishing a priority ranking among the devices. The circuitry also includes a call back system wherein if a given device is unready to receive data when addressed by a source device, such device will, when it is ready, call back the source device that was previously and unsuccessfully attempting to transfer data to it. The call back system is also adapted to permit a device to wait for response from a single one of the other devices until such other device responds and then to call back other devices that tried to address it while it was waiting for a response from the single device.

Single transmission bus data network employing an expandable daisy-chained bus assignment control line

Abstract: This disclosure relates to a network of stations having a single transmission bus. A bus assignment control line is daisy-chained to all of the stations to form a closed loop such that an assignment signal will circulate through the loop and return to the originating station after each station has been given an equal chance to be serviced. Stations of a lower priority can be attached to the bus in such a manner that the preceding station will direct the bus assignment control signal to the lower priority stations with a frequency less than the transmission of the assignment control signal to a succeeding higher priority station.

Undirectional looped bus microcomputer architecture

Abstract: A computing system architecture includes a central processing unit having a channel, arithmetic and logic unit, a plurality of working registers, and control logic; a plurality of local storage registers; a main storage; an executable control store; one or more input/output devices; and a multiplexed cycle steal and interrupt request common poll bus. The storage and input/output devices communicate with and are controlled by the central processing unit over a looped, or unidirectional bus and control channel including a bus in, a bus out, an address and a six-bit code bus, and a plurality of control lines. Bus out is operated to address the executable control store and main storage, and to provide data to the input/output devices and the local storage registers. Bus in is shared by the input/output devices and all storage devices and registers for transferring data and control information to the central processing unit. Bus in is also used by main storage to receive data from the input/output devices and from the local storage registers. The six-bit code bus addresses the input/output devices and the local storage registers, thus enabling overlapping of device or local storage data transfers with the accessing of executable control storage and main storage, and with instruction execution. The arithmetic and logic unit is time shared for data and input/output processing, register/register and storage/register transfers, shift operations, byte manipulation, address modification and program counter incrementing. Both cycle steal and interrupt requests are received by the central processor on the common poll bus.

Multiprocessor system with switchable address space

Abstract: In a data processing system comprising at least two microcomputers, one microcomputer (1) serves as a master to control the or each other microcomputer (2, 3 respectively) as a slave. In order to improve that utilization of the system the bus (4) of the master serves as a common bus and each slave has associated with it a buffer memory (5, 6 respectively) for the intermediate storage and transmission of data. The buffer memory can be connected, by means of an associated switching device (7, 8 respectively), alternately to the bus (9, 10, respectively) of the slave and to the common bus thereby switching the address field constituted by the buffer memory into the address space of the slave and into the address space of the master respectively. Furthermore, each slave has associated with it two interconnected input/output interfaces (11, 12 and 13, 14 respectively which serve for transmission of status signals concerning the master of the relevant slave. One of said interfaces is connected to the common bus, while the other interface is connected to the bus of the relevant slave. Each switching device is controlled by the corresponding input/output interface connected to the common bus, and hence by the master.

Distributed control memory network

Abstract: A computer-controlled distributed communication system in which there is a system controller and a plurality of group controllers all interchanging information over a system bus. Each group controller has its individual group bus for the exchange of information between stations of the group and the group controller. Each group controller shares a portion of its random access memory (RAM) with the system controller. When information is directed at approximately the same time to the RAM from a group central processing unit (CPU) bus and from the system CPU bus, the first to access the RAM is enabled to feed its information. Neither bus has any preference. The fed information is stored temporarily in a temporary storage of mailbox RAM in the group. Within the mailbox RAM, separate sections are provided for the storage of information for each direction of information transfer. The mailbox RAM is periodically interrogated during regular scans by the respective controllers to determine if information is stored awaiting transfer. An indication of stored information in a section triggers the transmission of information from the mailbox RAM when the destination bus is available. In this way, each processor can continue functioning without the imposition of a hold condition when access to the bus is not possible at that time.

Interface system wherein the interface is addressed before data transfer from a selected device

Abstract: An interface system for expanding the number of device input ports and compatable with the message format and bus structure of a standard interface, namely the IEEE standard 488, has address decoding logic which identifies the expansion system and is operative to select, in accordance with an incoming message on the bus, which of several ports is to transmit or receive messages via the bus. Under control of the port identification message and strobe signals obtained from the handshake control logic of the expansion system, a sequence containing a predetermined number of bytes of port data is transmitted to the bus. The port data bytes may be coded in various formats, desirably BCD, which is compatable with the digital output format of many devices which may be interconnected and interfaced by the expansion system with the bus. Manual control is enabled by the control messages which are received by the expansion system, such that the transmission of messages to the bus from the selected port or from any device connected to the bus may, if desired, be inhibited until the manual control is activated. Different control messages may be used to enable the transmission of different message sequences with or without activation of the manual control.

Communications subsystem having a self-latching data monitor and storage device

Abstract: A communications subsystem having a microprocessor coupled to an address bus and a data bus includes a latching register also coupled to the address bus and the data bus. The latching register is responsive to signals from the data bus and address bus for storing bits representative of a direct connect mode, a clear to send mode, and a bit oriented or byte control protocol mode.

Performance of a collision-free local bus network having asynchronous distributed control

Abstract: This paper provides an analysis of the performance of an access control scheme recently proposed by Eswaran, Hamacher, and Shedler for a local bus network. The control scheme is simple and asynchronous, and provides for collision-free communication among ports of the network. It is also efficient in the use of the bus bandwidth, in the sense that there is only a small fraction of time during which the bus is idle when there is at least one packet available for transmission. The performance analysis emphasizes the characteristics of bus access response times at the individual ports.

Time sharing device for the access to a main memory connected to a single bus between a central computer and a plurality of peripheral computers

Abstract: Such a device is necessary in an installation comprising fast working peripheral computers allowing to unload a central computer and having only one main memory. The device (5) comprises a searching circuit (6) allowing to detect which peripheral computer (41, 42, 43)... has asked to be connected to the single bus (3) to have access to the main memory (2) and a decision circuit (7) authorizing the peripheral computer to be connected to the bus (3) according to the utilization state of the bus (3) and giving the order to all other computers to disconnect from the bus when the access to the memory (2) is possible. Application: time sharing data processing and, particularly, telephony.

GAMMA - NET: Computer network coupled by 100 MBPS Optical Fiber Ring Bus - system planning and Ring Bus subsystem description

Abstract: Planning and design considerations are presented for a full scale high performance heterogeneous computer network coupled by a 100 MBPS optical fiber ring bus. The design goals of this system are efficient resource sharing and improved RAS. All common resources, such as processors, peripheral devices, terminals and file devices, are directly connected to the ring bus, instead of directly to a processor. This network includes two or more large computers of different types, a guide subsystem to manage common resources and to control their usage, peripheral and terminal control subsystems, and a gateway processor.

Separating system of faulty device

Abstract: PURPOSE:To completely disconnect a faulty device, by cutting off all devices to be controlled from a common bus while the signal which separates the faulty device is flowing to the common bus and accordingly preventing the transmission of noise to the common bus. CONSTITUTION:When a processor CPU detects that a fault arises at one of devices X1-Xn to be controlled, e.g., the device X1, the processor CPU sends a command to a non-individual controller F to set the corresponding flip-flop. With the output of the flip-flop, switches SW12-SWn2 are all cut off at a time and then controlled. As a result, all devices X1-Xn are cut off at a time from a common bus B. The processor CPU transmits the information to an individual controller Y to connect all nondefect devices X2-Xn to the bus B excepting for the favlty device X1.

WITS - A Coaxial Cable Bus Network for Medical Applications.

Abstract: Walter Reed ARMY Medical Center has been serving as a Army test bed for coaxial cable-based local area networks since early 1978. This particular network, called the WRAMC Information Transfer System (WITS), carries commercial television, FM radio, closed-circuit TV and maintenance intercom audio, as well as digital data. The technology has proven successful. Broadband coaxial cable systems provide an opportunity to realize communications architectures that are flexible, highly reliable, and inexpensive. They are particularly appropriate for use in medical facilities where applications change over time and when many and varied systems are required to interact together.

Bus priority control system in loop bus network system

Abstract: PURPOSE:To realize a loop bus priority control system which requires no special control unit on the loop by transmitting the bus control data including the priority level No. of the message plus the priority No. allotted to each host. CONSTITUTION:The bus control data is formed by providing the subpriority No. decided by the host as well as the level No. of the priority as shown in Fig. (a) to the message which is transmitted through each host processor 1. In case the messages of levels 2, 2 and 1 are produced at hosts I, IV and VIII each, the priority data produced at node processor 2 connected to each host turn to 23, 28 and 13 respectively to be transmitted in the form of the bus control data. Each node compared the data received from the preceding step node with the data transmitted from the node itself, and sends the received data to the next step only when the received data is higher in the priority than its own data. Otherwise the received data is disused. As a result, only data 28 generated at host IV has one circulation along the loop bus and then returns to host IV to acquire the using right for the bus.

Data processing system having modular bus structure and expandable configuration

Abstract: In a microprocessor system having modular bus structure and expandable configuration, several peripheral microprocessors (30 to 38) are connected to a central processor (1) through a common bus (11). Each peripheral may access the bus by means of an interrupt signal forwarded to the central processor through an interrupt line (12). In order to avoid conflicts among peripherals in accessing the bus, peripherals are ordered in cascade with decreasing priority. A peripheral which access the bus by means of an interrupt signal generates at the same time an inhibit signal on an output (IEO), which signal prevents peripherals having lower priority to emit the interrupt signal. Since the inhibition signal is propagated in cascade from peripheral to peripheral and in order to reduce the propagation time, a by-pass (400, 410 ...., 480) for the inhibit signal is associated to each peripheral and a propagation path (301, 302,...., 310) for the inhibit signal is established in form of a matrix instead of the cascade path used in the prior art.

A Distributed Computing Network for Real-Time Systems.

Abstract: : Partial interconnection, ring, and global bus topologies are examined in this document for use in a real-time distributed computing network. Message lengths and capacity allocation strategies for network links are evaluated in determining system performance based on average message delay. The data suggest a network topology for the application under study. Processor delays at each of the nine nodes in the network are introduced in a simulation model of a global bus network. Thus, link traffic and processor delays are utilized with message arrival rate, network bandwidth, and processor capacity parameters to arrive at a satisfactory computer system network for a real-time application. A methodology is developed whereby software requirements are determined in terms of the number of instructions executed. The desired system response time is established and software and hardware specifications may then be defined.