Showing papers on "Bus network published in 1982"

High speed bus architecture

Abstract: There is shown and described a high speed bus architecture which uses a common control bus and permits high speed data transfer between a plurality of active and/or passive users while reducing the system overhead structure which was previously required.

Microcomputer based distributed control network

Abstract: A distributed automated control network system consisting of a master host computer, network processing nodes for monitoring and control of work locations and a subhost node which interfaces the nodes and host computer. The subhost includes dual microprocessor configurations on a common bus, one for communications and one for control, operating 180° out of phase. Each node can be configured from a variety of modular subsystems on a common bus including modules for network control, data acquisition, digital and analog inputs and outputs, display terminals and the like in accordance with system requirements. The nodes communicate via two fiber optic channels, one operating clockwise and the other counterclockwise with foldback capability in the event of a fault. A conventional signal back-up is also provided.

High speed interconnection network for a cluster of processors

Abstract: A high speed interconnect network for a relatively large number of processors from as few as five to a hundred or more where the information transfers are serial-by-byte in a time multiplexed manner so that when one or more processors is ready to transmit, there will be an information byte being transmitted every clock time. A bus arbiter controls access to a local bus in a round-robin fashion when one or more than one processor is requesting access to the local bus. The bus arbiter also serves for connection to an overall global loop of bus arbiters each of which has a local bus and a plurality of individual processors.

Dual bus communication system

Abstract: A dual set of busses is used to provide close coupling between the data and voice services of the CS300 communication system. One of these busses is a time division multiplex bus arranged for communication between port access circuits, and the other bus is a packet-switched data processing bus used for interfacing both with the system peripherals and with the port access circuits. The port access circuits, as well as the faster peripheral circuits, can be connected to either or both busses thereby allowing for the efficient easy interchange of information.

Robot arm controller with common bus memory

Abstract: In a robotic apparatus having a manipulator arm including plural motors to move the arm to predetermined spatial positions and a control system for the arm, a common bus and common memory connected to the bus. The control system comprises respective microprocessor based controllers for each of the joints, microprocessor based computation means for performing the mathematical computation to control the trajectories of the arm and common microprocessor based coordinating control system for coordinating the activities of the other modular microprocessor based control system. Accessing routine is associated with the bus for providing each of the microprocessor based control system with direct, exclusive access to the bus during respective time intervals. The common memory serves as a depository for messages to and from the microprocessor based control system to enable intercommunication between the microprocessor based control system accessing the bus.

Digital data processor with high reliability

Abstract: FAULT-TOLERANT COMPUTER SYSTEM ABSTRACTA fault-tolerant computer system provides information transfers between the units of a computing module, including a processor unit and a memory unit and one or more peripheral control units, on a bus structure common to all the units. Information-handling parts of the system, both in the bus structure and in each unit, can have a duplicate partner. Error detectors check the operation of the bus structure and of each system unit to provide information transfers only on fault-free bus conductors and between fault-free units. The computer system can operate in this manner essentially without interruption in the event of faults by using only fault-free conductors and functional units. Arbitration circuits of unusual speed and simplicity provide units of the computing module with access to the common bus structure according to the priority of each unit. The units of a module check incoming and outgoing signals for errors, signal other module units of a detected error, and disable the unit from sending potentially erroneous information onto the bus structure.

Synchronous bus arbiter

Abstract: Un dispositif d'arbitrage de bus pour resoudre le probleme des requetes en concurrence d'acces a un bus (3) est associe a des lignes locales de commande de signaux (19) qui sont couplees a son 'maitre' associe (c'est-a-dire l'utilisateur du bus 1-N), et a des lignes de commande (6) du bus communes a toutes les autres unites Ces lignes locales de commande de signaux (19) comprennent un ensemble de lignes d'identification (25) definissant l'adresse (et le rang de priorite) du maitre associe, une ligne de requete (22) par l'intermediaire de laquelle les requetes des maitres ont acces au bus, une ligne de concession (23) par l'intermediaire de laquelle un maitre est informe qu'il possede la commande du bus, et une ligne de liberation (24) par l'intermediaire de laquelle le maitre informe le circuit de commande d'echange du bus (20) qu'il libere sa commande du bus. A bus arbitration system to solve the problem of queries in Access competition has a bus (3) is associated with local loop signal control (19) that are coupled to its 'master' associates (that is -a say user 1-N bus) and control lines (6) of the bus common to all the other units These local lines signal control (19) comprise a set of identification lines ( 25) defining the address (and rank priority) combines the master, a line of application (22) through the intermediary of which the queries of teachers have access to the bus, a concession line (23) through the intermediary which a teacher is informed that he possesses control of the bus, and a line of liberation (24) through the intermediary of which the master informs the control circuit for refilling the bus (20) that he frees his order the bus. Des lignes de commande qui sont communes a d'autres unites sur le bus comprennent une ligne d'occupation (32), par laquelle chaque circuit d'interface est avise que le bus est actuellement en service, une ligne d'horloge de bus (34) pour la synchronisation du fonctionnement des circuits de commande d'echange de bus (20), un ensemble de lignes de demande du bus (33) par l'intermediaire desquelles les adresses des utilisateurs demandant le bus sont acheminees et par l'intermediaire desquelles le probleme de priorite entre des demandes en conflit est resolu, et une ligne d'accuse de reception de selection (31) qui est utilisee pour mettre fin a la resolution de priorite une fois qu'il a ete determine quel est l'utilisateur demandeur qui possede la priorite la plus grande. control lines that are common to other units on the bus include a busy line (32), through which each interface circuit is advised that the bus is currently in service, a bus clock line ( 34) for synchronizing the operation of the control circuits of bus exchange (20), a set of bus request lines (33) through which the addresses of users requesting the bus and are conveyed by the intermediary where the problem of priority between conflicting requests is resolved, and a line accuses selection of reception (31) which is used to put an end to the priority of resolution once it was determined what the user applicant who possesses the highest priority. Le circuit de commande d'echange de bus (20) contient lui-meme un ensemble de logiques de combinaison (fig. 3) qui effectue un ensemble de taches d'entretien domestiques en utilisant les lignes de signaux de commande (6) de maniere a permettre a son maitre associe (1-N) d'obtenir la commande du bus (3) lorsqu'il est requis et, dans l'eventualite d'une pluralite de demandes simultanees de The control circuit bus exchange (20) itself contains a set of logical combination (Fig. 3) which performs a set of household cleaning stains using control signal lines (6) so a permit to his master associates (1-N) to obtain control of the bus (3) where required and in the eventuality of a plurality of simultaneous requests

Bus selection control in a data transmission apparatus for a multiprocessor system

Abstract: In a multiprocessor system having a main memory and a plurality of processors connected through common address bus, data bus and answer bus for data transfer, a data transmission apparatus is provided for each of the main memory and the processors and includes bus request control lines for transferring bus request signals and bus control signals, and a bus controller for separately controlling selections of the address bus, the data bus and the answer bus in response to the signals on the bus request control lines and the request signal. Overlapped processing such as data write and data write answer or data read and data read answer in one cycle is possible.

Access arbitration system to several processors or microprocessors with a common bus

Abstract: OF THE DISCLOSURE The invention relates to an access system to several processors having common resources by means of a common bus. For each processor this system comprises an arbitration means for access request conflicts. The arbitration means comprises access request processing means connected to the bus and to the processor and an access priority resolution circuit connected to the bus, to the access request processing means and to the processor. The resolution circuit is able to allocate mixed, cyclic or mixed fixed and cyclic priorities to the access requests. Application to the management of access requests for processors or microprocessors having common resources, such as e.g. memories. (Fig. 1)

Data processing system employing broadcast packet switching

Abstract: A data processing system employing broadcast packet switching and having a plurality of subsystems and a system bus for linking the subsystems. The subsystems are grouped within stations that are each enclosed by a computer cabinet. The system bus includes a star coupler, first and second external transmission lines connecting each station to the star coupler, and first and second internal transmission lines within each station that are coupled to the first and second external transmission lines. The subsystems within each station are each coupled to the first and second internal transmission lines by a system bus interface. The system bus interface monitors the system bus for an idle condition, and passes a message from its subsystem to the system bus only when it detects an idle condition on the system bus. Each message on the system bus includes a postamble that is garbled by any system bus interface that detects an error in any message on the system bus. Each subsystem has a local memory that includes a mailbox for storing header information of messages that are to be copied by that subsystem. DMA circuitry in each system bus interface manages the operation of the mailbox in its subsystem. In alternate embodiments, the star coupler may be a magnetic star coupler or an electrical star coupler, and the system bus may be comprised of two channels, each channel including a star coupler and pairs of transmission lines connecting each station to the star coupler.

Computer peripheral control apparatus

Abstract: A fault-tolerant computer system (10) provides information transfers between the units of a computing module, including a processor unit (12) and a memory unit (16) and one or more peripheral control units (20, 24, 28), on a bus structure (30) common to all the units. Information-handling parts of the system, both in the bus structure and in each unit, can have a duplicate partner (14, 18, 22). Error detectors check the operation of the bus structure and of each system unit to provide information transfers only on fault-free bus conductors and between fault-free units. The computer system can operate in this manner essentially without interruption in the event of faults by using only fault-free conductors and functional units. Arbitration circuits of unusual speed and simplicity provide units of the computing module with access to the common bus structure according to the priority of each unit. The units of a module check ncoming and outgoing signals for errors, signal other module units of a detected error, and disable the unit from sending potentially erroneous information onto the bus structure.

Bus arbitration logic

Abstract: An interactive computer terminal system having a bus for communication between elements of the system is disclosed having apparatus for assigning control of the computer bus on a predetermined order of priority. The CPU receives requests from computer system elements and assigns time slots for use of the system bus by arbitrating among various resources competing for access to the bus.

Bimodal bus accessing system

Abstract: A bus communication system has each of a plurality of bus interface units (BIUs) connected to a transmission bus at respective spaced locations along the bus. Each BIU includes a transmission system operable in both a contention mode and a token-passing mode. In the contention mode, the transmission system completes the transmission of information packets only after the BIU senses the bus and determines that no additional information packets are being transmitted on the bus. During the token-passing mode, the transmission system transmits an information packet only after the expiration of a time interval unique to that BIU and determined by the relative location both of that BIU and of the last BIU to transmit either an information or a start-up packet on the bus. A control system causes the transmission means to switch between the contention and token-passing modes of operation as a function of the transmission activity on the bus.

Fail-safe nodes for lightguide digital networks

Abstract: Lightguide digital networks that use fail-safe nodes made of an optical regenerator and optical couplers are described and analyzed. Every node in the network can regenerate or overwrite information traveling in a ring or bus network, and in the case of a power failure at one of the nodes, the network continues to function because the coupler keeps the continuity at the fatting node. Fail-safe nodes that operate at 16 Mb/s were built to implement a digital network of ring architecture. A description of the components is presented, together with an analysis of the design constraints of the different parts of the fail-safe nodes.

Access control of data transmission network

Abstract: A system for controlling access to a data transmission network of a bus configuration. After a communication unit has completed transmission of a message block, the communication unit transmits a synchronization signal over the bus. Each of the communication units of the network which has a message block for transmission responds to that synchronization signal by applying to the data bus the logical ones of the address of the associated data station, or of a virtual address resulting from an algorithm performed on that station address, the logical ones being applied in sequence during respective bit intervals. During bit intervals of the logical zeros of the station address, or of the virtual address, the communication unit monitors the bus. If during such monitoring the communication unit detects a logical one on the data bus, the communication unit terminates transmission of its logical ones and awaits the next synchronization signal. Thus, the communication unit of the highest station address, or virtual address, obtains control of the bus and only one communication unit transmits a message block at any one time, assuring there is no interference or collision of message blocks. On initialization of the system, if a communication unit monitors the data bus for a preset time without receipt of any transmission, the communication unit first transmits a logical one to the data bus and then transmits the logical ones of its station address to gain control of the bus, by the procedure mentioned above.

VLSI Wired-OR driver/receiver circuit

Abstract: Bidirectional communication upon a high performance synchronous (25 MHz line transfer rate) parallel digital communication bus interconnecting large numbers (up to 256 along 1 meter of bus) of very large scale integrated (VLSI) cirucit devices is supported by VLSI wired-Or driver/receiver (D/R) circuit elements synergistically operative under a two-time-phase bus electrical protocol for bus drive. During a first phase of approximately 10 nanoseconds all interfacing driver circuits additively drive, or pull-up, connected bus lines to a +3 v.d.c. logical High condition. During a second phase of approximately 20 nanoseconds during each 40 nanosecond cycle time D/R circuits present high impedance to charged bus lines for maintenance of such logical High and transmission of a logical "0", or else one or more D/R circuits drain line charge toward 0 v.d.c. for transmission for a logical "1". Two point driver to receiver, wired-OR, broadcast, and/or eavesdrop communication are supported for bus lines.

Method and device for transmission of digital data

Abstract: In a system comprising data-processing units, some of which are masters and others of which are slaves, all the units are connected to a common bus via interface circuits. Only the master units are capable of acquiring instantaneous control of the bus by means of a resource allocation device. By utilizing a set of three basic control signals carried by the bus, three distinct addressing modes can be established: master-to-master, master-to-slave, general master-broadcasting to all units in accordance with a number of chronologies and transmission modes. In an alternative embodiment, substitutions of addresses can be performed directly on the bus.

Optical passive bus control system

Abstract: An optical passive bus control system includes an access coordinator and control unit which is connected to the passive network in the same manner as other connected devices of the network. The access coordinator control means is located spatially close to the optical mixer, over connecting light wave guides which are as short as possible. The access coordinator and control unit contains a collision recognition device for recognizing an access collision, and includes means for implementing an asynchronous access operating mode in response to a collision recognition. A switch means is provided for emitting a signal to the bus, signifying a change to a synchronous operating mode in which no access collisions can occur.

Lookahead networks

Abstract: A fail-soft and easily reconfigurable interconnection network is proposed that can function like a bus or like a shift register ring. Its performance as a bus exceeds the performance of an Ethernet, and its performance as a ring is similar to that of a distributed local computer network (DLCN). It can be reconfigured to a sufficient degree to prune out faults or to partition the network into subnetworks that can use possibly different protocols that are the most suitable for the subnetwork. Its multiple-level priority arbitration appears very useful for mixed voice-data networks, to give guaranteed response times to voice packets. Finally, though it functions like a bus or shift register ring, it is physically connected like a tree; so its cost is linear and delay is logarithmic with the number of processors in the network, and it is relatively easy to install in a building by using practices similar to those used in telephone line networks. This paper describes functions of network-level and some data link and physical-level protocols and develops several key mechanisms to achieve ease of diagnosis and fail-softness.

Signal transfer arrangement using a bus as a storage device

Abstract: The signal transfer mechanism includes a plural-bit data bus (16) formed on an integrated circuit chip for transferring plural-bit binary data signals between plural-bit signal source registers (17, 18, 19, 26, 32, 35) and plural-bit signal destination registers (17, 18, 19, 26, 31, 32, 35) formed on the integrated circuit chip, and which are coupled to the plural-bit data bus (16) for respectively supplying plural-bit data signals to and receiving plural-bit data signals from the bus and a processor control unit (14) enabling one of the signal source register to put a plural-bit data signal onto the data bus (16) during a first processor control cycle and enabling one of the signal destination registers to take in this plural-bit data signal from the bus during a second and different processor control cycle. The inherent capacitance of the plural-bit data bus serves to store the plural-bit data signal during the first and second and any intervening processor control cycles.

Multiple computing systems and communication bus structure therefor

Abstract: A local system bus, including the necessary address, data and control lines, communicates a local central processor, memory, input/output and control resources forming a first computing system for executing processing operations. A controllable user bus interface circuit selectively couples the local system bus to a user system bus for selected communication therebetween. The user system bus includes the necessary address, data and control lines capable of communicating the user central processor, memory, input output and control resources, organized as a second computing system, for executing processing functions. The user bus interface circuit is controllable to permit undedicated local memory resources to be accessed by the user system bus for data transfer therebetween, undedicated user memory or input/output resource access by the local system bus for data transfers therebetween and isolation of the two system buses from each other. The controllable user bus interface circuit maintains asynchronous separation between the two system buses, which allows separate processing operations to be executed simultaneously on the two system buses whenever there are no transfers across the user bus interface circuit in progress.

Digital data processor with high reliability and method

Abstract: A fault-tolerant computer system (10) provides information transfers between the units of a computing module, including a processor unit (12) and a memory unit (16) and one or more peripheral control units (20, 24, 28), on a bus structure (30) common to all the units Information-handling parts of the system, both in the bus structure and in each unit, can have a duplicate partner (14, 18, 22) Error detectors check the operation of the bus structure and of each system unit to provide information transfers only on fault-free bus conductors and between fault-free units The computer system can operate in this manner essentially without interruption in the event of faults by using only fault-free conductors and functional units Arbitration circuits of unusual speed and simplicity provide units of the computing module with access to the common bus structure according to the priority of each unit The units of a module check ncoming and outgoing signals for errors, signal other module units of a detected error, and disable the unit from sending potentially erroneous information onto the bus structure

Information processing unit

Abstract: An N-bit (e.g. N = 4) memory (24) has separately accessible portions (A and B) which may be odd addresses and even addresses respectively. The even portion (B) is coupled by read and write buffers (21, 23) to two N-bit data buses (11,12) respectively so that one bus (11) is a read bus and the other (12) is a write bus for N-bit read/write operations. The odd portion (A) is coupled by read and write buffers (20, 21) and multiplexers (18, 19) controlled by a mode signal (13) so that for an N-bit data mode again the one bus (11) is a read bus and the other (12) is a write bus. For a 2N-bit mode, the one bus (11) is a write bus for the odd portion (A) and the other bus (12) is a read bus. In the N-bit mode the least significant address bit (16) selects the odd or even buffers. The other address bits (17) access both memory portions (A and B) for simultaneous reading or writing of 2N-bit data via both buses (11 and 12). In an alternative one memory portion is connected solely to one bus for both read and write. The other portion is connected to this bus in the N-bit mode and to the other bus in the 2N-bit mode.

Bus controlling system

Abstract: PURPOSE:To avoid that the control of a controller using a common bus becomes impossible by allowing data to flow to the common bus from an input/output device having a fault. CONSTITUTION:Each bus, a data/control bus D/C and address bus IOA which are shown at the left side of a bus adaptor BA are connected to a controller via a common bus B. While the buses as shown at the right side of the BA are connected to the input/output device (one of I/O1-I/On or m units of I/On+1- I/On+m). In a static state, a gate flip-flop G-FF is reset at each bus adaptor. Then ''0'' is delivered from an output terminal Q. With this output, line drivers DV1 and DV2 are inhibited together with a line receiver RV. In other words, the output has a high impedance. Thus the bus B and the adaptor BA are cut off from the input/output device which controls the connection with the controller.

High Speed Multi-Access Data Bus

Abstract: A 160 million bit per second (Mbps) data bus system is presented. This system provides a high speed data path between distributed subsystems through the use of microprocessor controlled access ports called nodes. Data bus system operation, node functions and high level node design are described. The system is modularly designed to allow data transmission rates from 20 to 160 Mbps in 20 Mbps steps. Each step is achieved by adding a 20 Mbps cable to the bus system, up to the maximum of eight cables. This modularity yields flexibility in tailoring the bus system transfer rate to the character of a particular application or to provide redundant cables for backup capability.© (1982) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Worst-case arbitration time in S-100-type computer bus systems

Abstract: The computer bus systems S-100 and Fastbus use a scheme consisting of extra logic circuits in each device and extra bus lines for arbitrating rapidly between two or more devices seeking to use the bus at the same time. The letter shows how to develop a table of priority numbers that make the arbitration time a maximum, and gives an expression for this maximum time in terms of logic-circuit and bus-propagation delays.

Bus constituting system

Abstract: PURPOSE:To connect an optional device to an optional position of an optional bus by providing a bus use right determining circuit which transmits a bus use permission signal and determines the directional property of a bus connecting circuit. CONSTITUTION:Central processing units 52 and 53, main storage devices 54 and 55, and input/output devices 56 and 57 are connected to a bus connecting circuit 58 through internal busses 50 and 51. A bus use right determining circuit 59 is provided. This determining circuit 59 accepts bus use request signals 60-65 from respective devices to determine the device for authorizing the use of a bus in accordance with a preliminarily determined priority and transmits corresponding one of bus use permission signals 66-71 to the device. The circuit 59 transmits bus transmission direction control signals 72 and 73 for controlling the signal transmission direction in the connecting circuit 58. Thus, an optional device is connected to an optional position of an optional bus.