Showing papers on "Bus network published in 1983"

High speed parallel bus and data transfer method

Abstract: A multiple bus system architecture and improved data transfer methods are disclosed for transferring data between a plurality of data processing resources. The bus structure of the present invention includes both a parallel and serial bus which interconnects data processing units and peripheral devices (collectively referred to as "agents") to permit the exchange of data and messages at high speed using a minimum of "handshake" events prior to the actual data transfer. Both the serial and parallel bus protocals are controlled by message control means coupled to each communicating agent. A local bus is coupled to processing agents within the system such that local memory and secondary processing resources may be accessed without impacting data traffic along the parallel bus. Direct access to resources coupled to the local bus of an agent from other bus agents is also controlled by the message control means.

Process control system with improved fault isolation

Abstract: A process control system includes redundant digital controllers and a plurality of input/output (I/O) modules for interfacing with remote field sensors and actuators. Bi-directional communication between controllers and I/O modules is achieved by a parallel wired, process I/O bus. Failures within the system, including the bus structure itself, that continually keep the bus active (i.e., in a low state) are isolated by a combination of software diagnostic routines for performing bus checkout and a unique quick disconnect feature that readily isolates the fault condition first between the I/O module nest area and the controllers, then, if necessary, to individual I/O modules. During fault isolation procedures, individual I/O modules may be disconnected from the bus while the values of field signals are simultaneously maintained to provide minimum process upset.

Dual path bus structure for computer interconnection

Abstract: A bus structure for use in a computer network requiring high availability and reliability of communications. Multiple bus paths (2A, 2B) are provided. When a transmission is to be made, under most circumstances the path is selected at random, with all paths being equally probable. Thus, failure of a path is detected quickly. Each host device in the network connects to the bus paths through an interface, or port (1). The task of path selection is carried out by the ports, independently of the host devices. The ports also detect path failures and automatically switch over to an alternate good path upon detection of such a failure, all without host involvement. Virtual circuit communications between hosts are transparent to path selection and switching, so the only indication to a host device of a path failure is a decrease in throughput. Most of the signal processing apparatus of each port (10, 20A, 20B) is shared by the paths, only one path being supported at any given time. Thus, the addition of a second bus path involves only minimal cost.

Distributed bus arbitration according each bus user the ability to inhibit all new requests to arbitrate the bus, or to cancel its own pending request, and according the highest priority user the ability to stop the bus

Abstract: A digital communication bus upon which arbitration is distributed in a multiplicity of communicable interconnected bus interface logics supports unique signals to each associated on user device and upon the bus. Arbitration inhibiting signals, called inhibit request signals, allow any one(s) user device(s) to inhibit the new entrance, via requests, into arbitration of all other bus interconnected bus interface logics and associated user devices. Arbitration among bus interface logics already registering requests continues in priority order. Each user device may, via a signal called retract request, deregister, or cancel, requests previously registered at the associated bus interface logics to arbitrate for ownership of the bus. Each user device may, via a signal called stop bus, cause continuous interface logics while being precluded from recognition that arbitration should ever be won. When the highest priority one user device so exercises the signal stop bus, then its associated bus interface logics always wins arbitrated ownership of the bus, but naught is known by, or done with, any user device of such ownership; effectively meaning the bus is stopped of normal data communication. Any bus-owning user device may communicate a signal, called priority disable, to the associated bus interface logic and upon a dedicated line of the bus, which signal, called priority disable, to the associated bus interface logic and upon a dedicated line of the bus, which signal postpones the recognition of the winning of arbitration in order that the current bus-owning user may longer retain ownership. Any particular bus interface logics may be, responsively to the setting of a flip-flop called the bus enable flip-flop by any external agency such as any User device or maintenance processor, disabled of any bus activity whatsoever, locking out the associated user device.

Self configuring bus structure for computer network

Abstract: A computer bus structure includes a plurality of separate bus segments on a mother board. Plugging in of each of a plurality of interface boards automatically connects the right-hand portion of a particular bus segment to the left-hand portion of an adjacent bus segment so that a local bus of the needed length is created from the separate bus segments by the plugging of a processor board and a plurality of interface boards into successive adjacent connector slots, respectively, of the mother board. Insertion of processor boards into a particular connection slot of the mother board prevents the two bus segments adjacent thereto from being connected.

Deadlock detection and resolution scheme

Abstract: @ in a communication system which includes a plurality of stations (23,24) interconnected for communications by a first bus (21), a second station (22) includes a device, such as a processor (25), and a resource, such as a memory (32) or a peripheral unit, interconnected for communication by a second bus (36) An interface mechanism (34) connecting the first bus with the second bus allows the device to access the first bus over the second bus, and allows a first station to access the resource via the first and second buses Deadlock detection circuitry (47) detects cotemporaneous attempts by the device to access the first bus and attempts by the first station to access the resource Deadlock resolution circuitry (26) responds to deadlock detection by disconnecting the device from the second bus to allowthe first station to access the resource, and by reconnecting the device to the second bus when the first station ceases to access the resource If the device is operating under program control, the deadlock detection and resolution are transparent to the program (Fig 1)

Multi-master communication bus system with parallel bus request arbitration

Abstract: Apparatus and a related method for regulating access to a communication bus to which multiple communication nodes are connected Control logic at each of the nodes determines which of them has priority to access the bus, by means of a parallel arbitration sequence in which all nodes contending for bus access participate Specifically, each contending node generates a relative priority node number and asserts it onto an arbitration bus All of the asserted node numbers are logically combined into a composite node number on the bus, and the winning node is determined in a bit-by-bit ripple comparison circuit at each node, the composite node number being compared with the locally generated relative priority node number Priority is determined in advance of data transmission, and synchronization and arbitration take place without any central or master control unit

Fault-tolerant power supply system

Abstract: A power supply system for use in a fault-tolerant computer having a main bus interconnecting several main bus elements, with at least one of the elements being capable of transmitting commands and receiving status information. The system includes a status bus which is coupled to the main bus. A control unit is associated with each bus element, such control unit including a voltage regulator connected to a primary source of power for providing regulated voltage to the associated bus element in response to commands received over the status bus from the main bus. The primary power source preferably includes redundant power supplies which provide voltage which is distributed over a pair of redundant voltage buses. Apparatus for sensing when a main bus element has seized the main bus may be included so that the bus element can be commanded by way of the status bus to release the main bus.

Multiprocessor computing system featuring shared global control

Abstract: A multiprocessor system comprises a plurality of stations interconnected by a system communication bus and cooperating in the performance of system tasks. Each station includes a plurality of addressable elements interconnected by a station communication bus. All stations are mapped into a common address space, with the elements of each station mapped onto like relative addresses in two subspaces of the address space: a subspace which is shared in common by all stations, and a subspace dedicated to the station whose addresses are the common subspace addresses in combination with a station-identifying address portion. The stations are symmetrical: like elements in all of the stations are mapped onto like relative addresses in their associated subspaces. Addressing within the system is self-referential: a station accesses one of its addressable elements by placing its common subspace address on the station communication bus. Each station's station bus is selectively interfaced to the system bus, and a station accesses an addressable element of another station by placing its dedicated subspace address on the station bus, interfacing its station bus with the system bus, and causing the other station to interface its station bus with the system bus. A station accesses an element of another station passively, without utilizing the intelligence, if any, of the other station to make the access.

Communication bus interface unit

Abstract: Apparatus and a related method for interfacing digital devices (20, 26; 38) with a communication bus (22a; b) in a local-area computer network. Each device (20, 26; 38) in a network is connected to the bus through a bus interface unit (24) providing the device user with the ability to establish a connection with another device by means of a simple CALL command that does not require the use of physical identifiers. The unit (24) also allows the user to enter a TALK mode in which a two-way conversation may be conducted over the network without the intervention of a host computer (26). A REMOTE command allows an unattended device to be controlled from another user site and also permits one user to connect two remotely located devices. A message command allows a message to be stored and held for a remote user, again without the intervention of a host computer (26).

Access control to a shared resource in an asynchronous system

Abstract: Independent asynchronous bus master devices share a common bus with control lines serially connecting each bus master in a daisy-chain contiguration A Bus Acknowledge signal is received by a local bus master which is thereby enabled to seize control of the bus without an input synchronization delay by first inhibiting synchronization means to prevent the passage of the Bus Acknowledge signal to a downstream device for a period of time sufficient to stabilize an output signal indicating such passage In that manner, the output signal may be used to control the immediate enabling of local bus seizure thereby avoiding local synchronization delay

A communication structure for a multiprocessor computer with distributed global memory

Abstract: An experimental multiprocessor computer was designed and built in order to explore the feasibility of certain internal communication mechanisms The system consisted of seven processing elements, each containing a part of the global memory connected to a local bus For each processor the global memory is seen as one single, linearly addressable structure The processing elements were all connected to a common, global bus, consisting of three separate busses in order to increase the capacity A bus selection unit was designed, capable of making a unique bus selection for each request, within a fraction of a memory cycle The experiments have shown that communication structures based on distributed global memory and global bus systems can be used efficiently for medium scale systems

Data link extension for data communication networks

Abstract: In a data communication network (100) wherein using units (104-111) contend for access to the network communication bus (160), data links (101-103) interface using units located remotely from the bus to the bus for communication such that the distances between the using units and the bus are rendered functionally transparent from the viewpoint of the bus. A data link (102) includes a network interface circuit (117) connected to and located near the using unit (108) for buffering communications passing between the using unit and the bus, a data transfer controller circuit (151) connected to and located near the bus for communicating on the bus on behalf of the using unit according to the communication protocol of the bus, a local fiber optic extension circuit (141) connected to and located near the data transfer controller circuit for emulating thereto the network interface circuit, a remote fiber optic extension circuit (125) connected to and located near the network interface circuit for emulating thereto the data transfer controller circuit, and an optical fiber link (131) connecting the fiber optic extension circuits.

Prioritized unidirectional distributed bus accessing system

Abstract: A plurality of bus interface units (BIUs), capable of placing information packets on a unidirectional transmit bus, are coupled to the transmit bus at locations spaced therealong. Each BIU comprises a transmit bus input port and a transmit bus output port, wherein the transmit bus input port of each BIU is coupled to the transmit bus output port of the next upstream BIU, and a receive bus input port connected to a receive bus. Each BIU includes a memory for storing at least one information packet to be transmitted and a control circuit associated with the memory. In a passive mode, the control circuit operates the BIU like a repeater, wherein packets received on its transmit bus input are reconstituted and retransmitted on its transmit bus output. In an active mode, the control circuit causes the BIU to transmit information packets stored in its memory. Each information packet may have a predetermined priority. The control circuit aborts transmission of an information packet whenever the BIU receives a higher or equal priority packet than it is transmitting and transmits the received packet in lieu of the aborted packet. Packets received during transmission, having lower priority than the packet being transmitted, are stored in memory for later transmission.

Master controller succession system for bus control access for data-communications local area networks

Abstract: An apparatus and a method which permits a plurality of master stations to be attached to a communications channel and to provide an arbitrating mechanism within each master by which one master station is designated as in control of the communications channel. The method overcomes the single point failure of the true master slave station by providing redundant masters. Furthermore, each station in the network is polled by a grant transmission at a constant interval of time irrespective of which master is in control of the bus to assure efficient utilization of the bus.

Multiple access data communication system

Abstract: In this data communication system, stations linked to a single line bus exchange information in a bit-serial asynchronous format in which transitions between stop and start signals mark beginnings of information bytes. The stations use a modified CSMA/CD protocol (carrier sense multiple access with collision detection) to obtain sending access to the bus. During information transfers, durations of stop signals are less than a predetermined limiting time length, but long enough to allow general purpose processing equipment at a station to participate directly in the real time process of information reception, thereby avoiding the need for having complex and costly adapting equipment interface between the bus and such processing equipment. When any transmission concludes, the bus remains at the stop signalling level. By conditioning detection of bus availability on timeouts conducted while the bus is in this condition, stations then ready to transmit avoid interfering with on-going transmissions. After timing out, any station may begin transmitting. At this same time, all stations monitor the bus receptively. If a station not currently sending detects a start-stop transition, its processor is interrupted and directly examines the following information byte signals. If a sending station detects a transition, its processor acts to sense for bus collision by comparing the byte last transmitted with the byte last received from the bus. If collision is detected, the sending process is aborted and the timeout process for detecting bus availability is repeated. If collision is not detected, the sending process continues.

Method and apparatus for bus contention resolution

Abstract: ' method and apparatus for bus contention resolution for use in a digital communications system wherein a plurality of communications controllers (3000) are connected to a shared bus (100) for transmitting information in frames. A priority field is included in each transmitted frame. The bus is monitored such that any time the bus is conveying a frame, the priority field of that frame is known at each of the communications controllers. A given communications controller makes a determination based on the priority fields of a new frame and a present frame being actively conveyed by the shared bus so that the new frame is of higher priority than the present frame. Upon such a determination, the given communications controller transmits the new frame. In accordance with a second aspect of the method and apparatus, the bus has the characteristic that when any communications controller connected thereto transmits a predetermined logic value, the bus conveys that predetermined logic value regardless of logic values transmitted by other communications controllers. Each communications controller monitors the bus and counts the number of consecutive bits conveyed thereon having the predetermined logic value. Any communications controller that desires access to the bus consecutively transmits the predetermined logic value a number of times such that the predetermined logic value is conveyed a fixed number of times on the bus. The communications controller then transmits a unique bit sequence but terminates transmission when a difference is detected between a bit transmitted by that communications controller and a bit contemporaneously conveyed by the shared bus.

Method for extending a parallel data bus

Abstract: A bus extender which accepts data from a parallel data bus and extends the bus by means of a serial link to another parallel bus. The bus extender comprises a local and remote station or terminal, each having a transmit and receive section. A transmit terminal receives a data frame from the parallel bus and decomposes the frame into data and management sub-frames. The local and remote terminals exchange management sub-frames, thereby starting the transmission process. A data sub-frame is then transmitted from the local to the remote station and a management sub-frame is returned from the remote station indicating receipt of the data sub-frame. Other sub-frames may be exchanged for specialized purposes, such as polling and error signalling. Specialized messages may be identified by tagging sub-frames with message codes. At the remote station, the original management and data bits are reassembled into a single data frame with placement of the bits in the same order as originally appeared at the local station. The new frame is then transferred on the data bus with all bits in parallel. The bus extender appears transparent to the two parallel bus sections.

Memory-programmable control

Abstract: A multiprocessor system having a memory-programmable control of the type having a processor unit, coupling memories and input and output modules for transferring signals to and from a process which is to be controlled. Each processor unit is provided with a subprogram and a data memory which can be accessed directly, and a bus control unit releases access to the common system bus always for only one of the processor units. The access sequence and the access duration of the individual processor units to the common bus, via which the signals run to and from the controlled process, are fixed in a bus assignment matrix. In this manner, simple synchronization of the processor units is achieved. Moreover, guaranteed reaction times with respect to the process are possible. In addition to the duration, sequence, and frequency of the bus access of each processor unit in a bus cycle, the latest number bus window which must be seized by each processor unit can also be monitored by a bus monitoring device, thus insuring that guaranteed reaction times are possible.

Direct memory access revolving priority apparatus

Abstract: In a terminal system comprising a central processor subsystem, a memory subsystem and a plurality of peripheral subsystems, all connected in common to a system bus, the system bus timing is divided into a plurality of fixed times including a central processor (CPU) bus cycle and a plurality of Direct Memory Access (DMA) bus cycles. The central processor subsystem communicates with the memory subsystem during CPU bus cycles and the peripheral subsystems communicate with the memory subsystem on DMA bus cycles. Particular peripheral subsystems are assigned to particular DMA channels. These DMA channels communicate with the memory subsystem on particular DMA bus cycles which are operative in a revolving priority, with the first DMA bus cycle occuring after the last DMA bus cycle of the previous sequence of DMA bus cycles. A plurality of peripheral subsystems are wired to a particular DMA channel in a daisy chain fashion with the peripheral subsystem wired closest to the system bus having top priority. The peripheral subsystem having top priority may be wired either to relinquish the assigned DMA bus cycle after communicating with memory or "hog" the assigned DMA bus cycle.

Bus grant circuit

Abstract: A bus grant circuit for controlling access by a digital device connected to a common bi-directional bus and a bus arbitration system incorporating such circuit. The bus arbitration system comprises a common bus request, a common bus busy line, a bus grant line daisy-chained through each device which may request bus control and a bus arbitrator which asserts a signal on the bus grant line in response to a bus request signal and the absence of a bus busy. Each device which may request bus control includes an associated bus grant circuit comprising a first flip-flop responsive to the input of the bus grant signal and to an internal bus request signal from the associated device to set when the bus grant signal is asserted and the internal bus request signal is not asserted, allowing the bus grant signal to be passed on, a second flip-flop responsive to the input of the bus grant signal and to the internal bus request signal to set when the bus grant signal and the internal bus request signal are asserted, allowing the associated device to the control of the bus, and associated logic for preventing both circuits from being set simultaneously.

Priority control method and apparatus for common bus of data processing system

Abstract: In a system of the type in which processing units and terminal devices are connected to a common bus so that messages can be transmitted and received between these units and devices via the bus, the processing units and the terminal devices are connected to the common bus by node processors. A bus control method, the so-called "contention system", is adopted in which the first node processor starting a transmission of a message from the node processor to the common bus is given the right to transmit the message when a plurality of node processors have transmission messages to send. When transmissions are simultaneously started by two or more node processors, they are inhibited, and the messages to be transmitted are assigned priorities and are retransmitted by the corresponding node processors after the lapse of waiting times of different values which are set in advance in accordance with the priorities.

Preemptive bid communication system

Abstract: In a bus communication system, a unidirectional transmit bus is coupled to a unidirectional receive bus such that information packets leaving the transmit bus are placed on the receive bus. A plurality of bus interface units (BIUs) are coupled in series at spaced locations to the transmit and receive buses. The BIUs communicate with one another by transmitting information packets on the transmit bus and receiving transmitted information packets from the receive bus. A BIU transmits an information packet when both buses are silent. In the event of a collision between two information packets, downstream BIUs abort transmission and defer to the most upstream BIU having transmitted. Each BIU having had a transmission aborted attempts to gain access to the bus by placing a beep on the transmit bus which informs other BIUs that a BIU requests access to the bus. Only the most upstream BIU requesting access is permitted to transmit a packet. This process is repeated until all BIUs having had a transmission aborted have transmitted their aborted information packets.

Time-locking method for stations which form part of a local loop network, and local loop network for performing this time-locking method

Abstract: A method for use in a local loop network comprising a plurality of stations which are distributed along a bus, each station being connected to the bus via a coupler which is inserted in the bus. The time-locking method for these stations comprises a transmission phase during which a looping unit which is also inserted in the bus transmits a frame (transmission frame) which consists of a synchronization word and one or more slots which initially do not contain data and which correspond to the time position occupied by each of the stations, a receiving phase during which the demodulation of the transmission frame by the master clock of the looping unit is performed after the retransmission in the form of a frame which is referred to as the receiving frame, of this frame to the coupler of each of the successive stations and, after the receiving phase, new transmission and receiving phases until the insertion of the data on the bus by each station during a transmission phase takes place with the desired accuracy.

Distributed time division multiplexing bus

Abstract: High density time division busses suffer from many problems, one of which is that impedance discontinuities (LO, CB; Fig. 10) cause signal reflections to occur along the bus. These reflections, in turn, affect the settling time and noise margins of the bus and thus reduce the time "window" in which valid signals may be received. There is disclosed a transmission bus structure (Fig. 12) which allows for bidirectional, multi-port operation by using current drivers (Do/, D1, D3) instead of the traditional voltage drivers for placing data signals on the bus (Lo/, L1, L3). The transmission bus is designed in a manner which allows transmission and reception from a signal clock (501; Fig. 5) on the same clock edge, thereby substantially increasing the time allowed for transmission response and also simplifying the clock distribution requirements (Fig. 12).

Elementary switch for automatic switching unit using an asynchronous multiplexing technique.

Abstract: The elementary switch of the invention includes, in one embodiment, a single memory 10D associated with an input bus 26D connected to input circuits 8D, and with an output bus connected to output circuits 27D. Each bus is handled by a handler 16D, 31D. The input bus is connected to a translation memory 14D. The single memory is associated with a stack of free cells 28D, and each output circuit is associated with a stack of occupied cells 29D. Application: public or private telephone.

Data processing system having unique bus control protocol

Abstract: In a data processing system which uses a common bus for communication of address and data information among a plurality of system components, a bus timing technique uses a clock signal having a transfer time period which comprises a plurality of subperiods which requires address transfer to take place during a first selected group of subperiods and data to be transferred during a second selected group of subperiods with idle subperiods in between. A first control signal is generated by the data receiving or data supplying unit in order to inhibit access to the bus until such transfer is completed and a second control signal can be provided to lock-in bus access by such unit if desired for more than one transfer period. Appropriate priority is arranged for bus access among selected system components whether the common bus system has a single bus for use with a single port memory or a dual bus for use with a dual port memory.

Interface for managing information exchanges on a communications bus

Abstract: An interface for managing information exchanges on a communications bus between at least one control unit and peripheral units, or between said peripheral units. The exchanged information includes data and a destination address of said data. The interface is characterized in that it comprises for each unit, data transmission circuitry connected to the unit and to the bus for managing the data transmission on the bus to the unit having the destination address, data reception circuitry connected to the units and to the bus, for managing the reception of data by the unit having the destination address, and management circuitry for managing the addressing of the units during exchanges and in particular for managing access priorities to the bus, without necessitating the intervention of the control unit. This interface can be used for information exchanges between processing or measuring units.

Universal coupling means

Abstract: A universal coupling unit for linking processing systems incorporating computers or processors with at least one peripheral unit. Each processing system has at least one processor and an exchange bus for exchanging information with the peripheral unit. The coupling units comprise bus controllers connected respectively to the exchange buses and to a local bus, itself connected to the peripheral unit by circuits for controlling exchanges of data and for processing control and state information. The bus controllers are able to manage the access protocols to the exchange buses, the information exchanges on the exchange buses and on the local bus, as well as any request made by a processor for access to the local bus. The control units comprise a microprocessor for managing the priorities of the access requests of the processors and the processing of controls and states contained in the information exchanged on the local bus. Selection devices are connected to the bus controllers and controlled by the management microprocessor for selecting, as a function of the priorities, the controller able to ensure a data exchange on the local bus. An input and output buffer register is connected to the local bus and to the peripheral unit for receiving the data to be transmitted to the peripheral unit for receiving the data to be transmitted to the peripheral unit or for receiving the data to be transmitted to one of the processors.