scispace - formally typeset
Search or ask a question

Showing papers on "Bus network published in 1984"


Journal ArticleDOI
Fine1, Tobagi
TL;DR: In this paper, the authors present many implicit-token DAMA schemes in a unified manner grouped according to their basic access mechanisms, and compare them in terms of performance and other important attributes.
Abstract: Local area communications networks based on packet broadcasting techniques provide simple architectures and efficient and flexible operation. Various ring systems and CSMA contention bus systems have been in operation for several years. More recently, a number of distributed demand assignment multiple access (DAMA) schemes suitable for broadcast bus networks have emerged which provide conflict-free broadcast communications by means of various scheduling techniques. Among these schemes, the Token-Passing Bus Access method uses explicit tokens, i.e., control messages, to provide the required scheduling. Others use implicit tokens, whereby stations in the network rely on information deduced from the activity on the bus to schedule their transmissions. In this paper we present many implicit-token DAMA schemes in a unified manner grouped according to their basic access mechanisms, and compare them in terms of performance and other important attributes.

155 citations


Journal ArticleDOI
TL;DR: A two-phase algorithm for finding the maximum of a set of values stored one per processor on an n X n array of processors that uses conventional links during the first phase and the global bus during the second is presented.
Abstract: The problem of finding the maximum of a set of values stored one per processor on an n X n array of processors is analyzed. The array has a time-shared global bus in addition to conventional processor-processor links. A two-phase algorithm for finding the maximum is presented that uses conventional links during the first phase and the global bus during the second. This algorithm is faster than algorithms that use either only the global bus or only the conventional links.

151 citations


Patent
03 Jan 1984
TL;DR: In this article, a microprocessor device used as an adapter for a communications loop of the closed-ring, token-passing, local area network type is presented, where each station on the ring has a host processor with a host CPU, a main memory, and a system bus.
Abstract: A microprocessor device used as an adapter for a communications loop of the closed-ring, token-passing, local area network type. Each station on the ring has a host processor with a host CPU, a main memory, and a system bus. The microprocessor device, operating relatively independent of the host CPU, is coupled to the main memory by the system bus and includes a local CPU, a local read/write memory, an on-chip timer, a local bus and a bus arbiter. A transmit/receive controller is connected between the ring and the microprocessor device. This controller is coupled to the local bus to directly access the local read/write memory, also under control of the bus arbiter. The local CPU executes instructions fetched from a ROM accessed by the local bus, so the local CPU instruction fetch, the direct memory access from the transmit/receive controller for transmitting or receiving data frames, and the access from the host CPU for copying transmitted or received message frames, all contend for the local bus. Bus arbitration with appropriate priorities is used to control access to the local bus. The on-chip timer accessed by the local bus provides the time period used to monitor and control the communications protocol.

119 citations


Patent
18 May 1984
TL;DR: An initial polling sequence for configuring a modular computer system employing a system bus for interconnecting the CPU and various modules attached to the bus is described in this article. But it does not specify a polling sequence.
Abstract: An initial polling sequence for configuring a modular computer system employing a system bus for interconnecting the CPU and various modules attached to the bus. At the beginning of the polling sequence, a bus base address register in each module is preset to a port 0 address by the CPU. A POLL signal is generated by the CPU and intercepted by the closest module, which responds by placing a module identification character on the data lines of the system bus. The CPU receives the module identification character, stores this character in a table and issues a bus base address for that module. Upon receipt of the bus base address, the module presently active in the polling sequence issues a POLL command to the next module on the system bus. The poll sequence is repeated until all modules have been assigned and have received a bus base address.

107 citations


Patent
Kowalski Joseph L1
02 Mar 1984
TL;DR: In this article, a multiple device serial data bus and signalling scheme for inter-peripheral communication at a data rate established by a bus control unit is described. And an arbitration scheme is provided to eliminate bus contention if several units request service simultaneously.
Abstract: A multiple device serial data bus and signalling scheme is described The serial data bus allows for inter-peripheral communication at a data rate established by a bus control unit Clocking information is extracted from data communicated from the bus controller to the peripheral devices Additional conductors for clock information are not required In addition an arbitration scheme is provided to eliminate bus contention if several units request service simultaneously The multiple device serial data bus is utilized on an as required basis and may communicate information at a variety of data rates

97 citations


Patent
Bruce A. Loyer1
24 Dec 1984
TL;DR: A serial communications interface for coupling a physical layer such as a modem to a media access control layer in a token bus network provides data and station management information there between on a plurality of bidirectional data lines providing management functions and a unique serial bus for control transfer in addition to communications data as discussed by the authors.
Abstract: A serial communications interface for coupling a physical layer such as a modem to a media access control layer in a token bus network provides data and station management information therebetween on a plurality of bidirectional data lines providing management functions and a unique serial bus for control transfer in addition to communications data.

64 citations


Patent
23 Aug 1984
TL;DR: A high speed data transfer method and apparatus is described in this paper, where the bus controller sequences through these address pairs at an aggregate rate greater than some of the devices' ability to transfer data to enhance data transmission speed on the bus.
Abstract: A high speed data transfer method and apparatus. A high speed data bus includes separate data transfer and master control bus portions. A system host computer loads a sequence of source and destination addresses corresponding to communications units coupled to the bus into memory in a bus master controller. The bus controller sequences through these address pairs at an aggregate rate greater than at least some of the devices' ability to transfer data to enhance data transmission speed on the bus. Bus cycles are allocated to devices on the bus according to a scheme dependent on those devices ability to utilize the bus. High speed devices are allocated a greater number of bus cycles per unit time than slower devices.

64 citations


Patent
01 Feb 1984
TL;DR: In this paper, a chain of arbitration devices are interconnected in a chain by a priority bus of branched binary structure divided into m lines connected, within each device, to a logic network that is also connected to an internal m-conductor bus extending from a priority-code register.
Abstract: A circuit arrangement for deciding concurrent requests for access to a common data bus emitted by a number n=2 m of components of different ranks, specifically multiprocessor elements, comprises n mutually identical arbitration devices respectively associated with these components. The arbitration devices are interconnected in a chain by a priority bus of branched binary structure divided into m lines connected, within each device, to a logic network that is also connected to an internal m-conductor bus extending from a priority-code register. The priority bus, whose lines are normally at zero potential, is connected in any given device to the register thereof in the presence of an access request from the associated component whereupon its logic network determines whether the code on that bus equals the contents of the register; if so, the associated component is enabled by a control unit of the device to access the data bus. If, however, a simultaneous access request from a higher-ranking component causes another arbitration device to energize the priority bus, the code emitted by that other device overrides that of the first-mentioned device whose logic network therefore detects an inequality. A cascaded connection of the control units of the several arbitration devices enables a decrementer in each device to establish priority codes of progressively lower rank along the cascade in an initialization phase; the logic network also modifies, at the beginning of each operating cycle except during prolonged seizure of the data bus by any component, the priority code initially assigned to each arbitration device in order to give precedence to nominally lower-ranking components.

42 citations


Patent
10 Feb 1984
TL;DR: A token-passing ring network as discussed by the authors employs multiplexing circuitry for connecting each node to the bus on at least one of a plurality of simultaneously operating bus channels, each bus channel operates independently of each other bus channel and each channel has associated therewith, its own token.
Abstract: A token-passing ring network, having a plurality of nodes connected to a bus loop, employs multiplexing circuitry for connecting each node to the bus on at least one of a plurality of simultaneously operating bus channels. Each bus channel operates independently of each other bus channel and each channel has associated therewith, its own token. The multiple channels are arranged on a single transmission medium and an amplitude multiplexing receiver and transmitter circuitry provide the plurality of channels on the medium.

40 citations


Patent
13 Nov 1984
TL;DR: In this article, an apparatus for providing masterless collision detection in a communication network includes a distinct data transmission bus and a distinct collision detection reference bus, which is monitored by each element to ascertain the existence of a change in the voltage which results in either the enabling or disabling of data transmission on the transmission bus by that element.
Abstract: An apparatus for providing masterless collision detection in a communication network includes a distinct data transmission bus and distinct collision detection reference bus. A voltage on the reference bus is monitored by each element to ascertain the existence of a change in the voltage which results in either the enabling or disabling of data transmission on the transmission bus by that element.

37 citations


Journal ArticleDOI
TL;DR: An architectural approach is described that draws upon and integrates the advantages found separately in these three different architectures, while avoiding the major disadvantages found in any one, resulting in a wide-area network capability.
Abstract: LOCAL AREA NETWORKS are currently enjoying tremendous popularity as a means for providing wideband interconnection and communications among data terminals, host computers and other types of digital equipment located throughout a single building or a campus of buildings. Such networks are typically based on bus, ring, or star architectures, each of which manifests its own set of advantages and disadvantages. In this paper, an architectural approach is described that draws upon and integrates the advantages found separately in these three different architectures, while avoiding the major disadvantages found in any one. This new architecture employs a centrally located short bus that provides an extremely efficient packet-switching service to the devices attached to the network. Bandwidth on the short bus is dynamically allocated in response to instantaneous demands by means of a highly efficient but flexible prioritybased bus contention scheme. The approach permits multiple priority classes with fair allocation of bandwidth within each class, along with a capability for integrated circuit and packet switching. The architecture can also make use of existing twisted-pair building wiring, and at the same time take advantage of emerging optical-fiber technology. In addition, the architecture provides a means to expand the network beyond a local area, resulting in a wide-area network capability.

Patent
10 May 1984
TL;DR: In this article, the authors propose a method of providing access to a multiplexed data bus having a plurality of data processing units coupled thereto, where each unit self-assigns sequence numbers for identification purposes.
Abstract: A method of providing access to a multiplexed data bus having a plurality of data processing units coupled thereto. Each unit self-assigns sequence numbers thereto for identification purposes. The unit having the lowest sequence number obtains immediate access to the bus and may relinquish the bus by transmitting a control word, or token, with an incremented sequence number. All units receive the token but only the unit having the incremented sequence number gains access to the bus. The token passing continues through the series of sequence numbers and then recycles when no unit accepts the token (bus timeout). A newly added unit self-assigns a sequence number equal to the one transmitted prior to the bus timeout and thus acquires bus access on the next cycle. If a unit in the cycle fails, a bus timeout occurs mid-cycle and the access loop recycles. The units not gaining access to the bus during the cycle decrement their sequence numbers to close the gap, and hence gain access on the next cycle. The method allows for continuous system operation if units are added or deleted, without interrupting bus operation.

Patent
30 Apr 1984
TL;DR: In this paper, a packet bus is operated under the direction of a bus controller which communicates with the ports to arbitrate access to the packet bus for packet transmission for data transactions and voice communications.
Abstract: Data transactions and voice communications are facilitated in a packet switching system including a group of ports each of which is capable of exchanging inter-destined and intra-destined information signals via a packet bus. The packet bus is operated under the direction of a bus controller which communicates with the ports to arbitrate access to the packet bus for packet transmission. Arbitrating access to the packet bus for pseudo-synchronous and asynchronous signal communications includes the steps of polling the ports within a period of time for high and low priority, transmission requirements. In response to each high priority requirement transmission over a predetermined number of consecutive bus cycles is granted by the bus controller within a predetermined period of time for pseudo-synchronous transmission of signals from each of the corresponding ports one after another. In response to each lower priority requirement, transmission over an indefinite number of consecutive bus cycles is granted by the bus controller for asynchronous transmission of signals from at least one of the corresponding ports. The preceding steps are repeated with a frequency such that high priority grants occur at a uniform rate that is consistent with a sampling rate of digitized voice communications being divided by one less than the predetermined number of consecutive bus cycles.

Patent
23 Apr 1984
TL;DR: In this article, a data communication network over which data handling devices can transmit and receive packets among themselves having a bus, a number of sub-networks (each having interfaces for connecting devices connected to each sub-network), a concentrator for connecting each interface to the bus, each concentrator having a transceiver for transmitting, to the buses and to devices connected in each subnetwork, packets originating from devices within a subnetwork (transmitted packets), and for receiving from the bus packets originating in other sub-nets (received packets), collision avoidance circuitry for monitoring transmission attempts
Abstract: A data communication network over which data handling devices can transmit and receive packets among themselves having a bus, a number of subnetworks (each having interfaces for connecting a number of devices to each subnetwork), a concentrator for connecting each interface to the bus, each concentrator having a transceiver for transmitting, to the bus and to devices connected to each subnetwork, packets originating from devices within a subnetwork (transmitted packets), and for receiving from the bus packets originating from other subnetworks (received packets), collision avoidance circuitry for monitoring transmission attempts by devices connected to the subnetwork, for detecting competing transmission attempts that would create a collision on the subnetwork, and, upon such detection, permitting a selected attempt to enter the subnetwork, while preventing other attempts from entering it, collision detection circuitry for monitoring the bus and preventing all attempted transmissions from entering the bus whenever a packet from another subnetwork is present on the bus. In another aspect the interface means and the concentrator means include a network interface unit and a further interface unit.

Patent
18 Jan 1984
TL;DR: In this article, a priority system for controlling the sequence in which requests made by modules, connected in parallel to a common bus, for access to the common bus is granted is presented.
Abstract: A priority system for controlling the sequence in which requests made by modules, connected in parallel to a common bus, for access to the common bus is granted. A bus busy line is maintained at a first predetermined voltage if the common bus is not busy, and at a second predetermined voltage if the common bus is busy. A control and timing logic unit in each module senses the voltage on the bus busy line and permits access by the module to the common bus if the bus is at the first predetermined voltage (not busy). The control and timing logic unit then drives the voltage on the bus busy line to the second predetermined voltage, to indicate that the common bus is in use, thereby prohibiting access by other modules.

Patent
Radu Alexandru1
21 Nov 1984
TL;DR: A bus structure for an image processing system connecting a plurality of devices capable of transmitting and receiving packets of N data words serially on N sub-buses is described in this article.
Abstract: A bus structure for an image processing system connecting a plurality of devices capable of transmitting and receiving packets of N data words serially on N sub-buses wherein the data sub-buses are spatially multiplexed and an address bus is time multiplexed.

Patent
28 Jun 1984
TL;DR: In this paper, a distributed data processing system is described, which features independent processors of varying types chosen in accordance with a specific task to be performed, all of which are connected by a serpentine data highway bus.
Abstract: A distributed data processing system is disclosed which features independent processors of varying types chosen in accordance with a specific task to be performed, all of which are connected by a serpentine data highway bus. Each of the processors has access to the bus at stated intervals in a time division multiplexing scheme and outputs onto the bus data such as process control data according to a predetermined sequence. The system is also operated in a democratic mode during which additional data items may be output onto the bus as required. Each of the data processors is capable of determining which data items its operations are concerned with, and in the preferred embodiment, the system comprises timekeeper processors which output system clock signals over the bus in the same way as process control data. The individual processors each examine all the messages on the bus to determine if they are of local interest, and copy them to local memory if desired. In the preferred embodiment, at each distributed location a data highway processor performs the communications function, while a functional processor monitors and controls local functions.

Journal ArticleDOI
R. Männer1, B. Deluigi1, W. Saaler1, T. Sauer1, P.V Walter1 
TL;DR: An overview of the Polybus system, details of its operation and a comparison of some implementation details with other standard solutions are presented.

Patent
14 May 1984
TL;DR: In this paper, the authors proposed a survivable bus network consisting of multiple busses, bus isolation device (BIDs) and two types of network interface processors (NIPs).
Abstract: Enhanced availability and survivability of communications between geographically remote locations with a minimum of redundancy of transmission facilities and media is provided by a survivable bus network capable of providing continued interprocessor or other communications in the event of multiple bus outages. It consists of multiple busses, bus isolation device (BIDs) and two types of network interface processors (NIPs). The BIDs electrically isolate bus segments on either side of a connection so that if a fault occurs only the segment containing the fault will be affected. The first type of NIP connects to one bus and performs the usual function of providing an electrical and software interface between the network and one or more subscriber processors. The second type is a bridge which performs these same functions but connects to two busses and has the capability to transfer traffic as it appears on either bus to the other. The network provides increased survivability in the event of failed segments but does not entail the expense of a fully redundant system.

Journal Article
TL;DR: Heuristic network optimization as one of the available methodologies to improve transit networks is described and a wide range of approaches are revealed that are generally theoretically sound, have reasonable potential for generating improved networks, and are computationally and otherwise feasible.
Abstract: Changes in urban land use and travel demand have created the need to restructure many existing mass transit networks. Heuristic network optimization as one of the available methodologies to improve transit networks is described. The characteristics and results of the algorithms developed in Europe are summarized and a short description of the American algorithms is given. The potential for applying network optimization methodologies in the context of small to medium-sized American cities is evaluated. The review and evaluation of 13 heuristic methodologies revealed a wide range of approaches that are generally theoretically sound, have reasonable potential for generating improved networks, and are computationally and otherwise feasible. Application of an unproven new algorithm by Mandl to the bus network for Madison, Wisconsin, and the light rail network for Duesseldorf, West Germany, showed that a fairly complex heuristic algorithm can be implemented quickly and easily. Mandl's algorithm, however, did not generate an improved network, primarily because the initial computer-generated network does not follow demand. Better results were obtained with two other heuristic methodologies that have been applied to the Duesseldorf network. The Madison and Duesseldorf applications form the basis for recommendations for further improvement of heuristic methodologies.


Patent
Joseph Pumo1
13 Nov 1984
TL;DR: In this paper, a bi-directional bus isolation circuit couples the logic state present on a primary bus to a polysilicon secondary bus or the logic states present on the secondary bus to the primary bus in response to a select signal.
Abstract: A bi-directional bus isolation circuit couples the logic state present on a primary bus to a polysilicon secondary bus or the logic state present on the secondary bus to the primary bus in response to a select signal. A first NOR gate has one input coupled to the primary bus and a second input for receiving the select signal. A first output transistor couples the secondary bus to ground in response to the first NOR gate providing a logic high output. A second NOR gate has a first input coupled to the secondary bus, and a second input for receiving the select signal. A second output transistor couples the primary bus to ground in response to the second NOR gate providing a logic high output.

Journal ArticleDOI
TL;DR: The second bus is shown to add substantially to the versatility and power of the system and provides the means by which a single processor system can be upgraded into a distributed processor network without making the special interfaces designed for the single processor obsolete.
Abstract: This modular microprocessor system can be used to create a wide range of custom‐tailored computer systems out of a standard set of active modules. New modules can be easily incorporated into the system as the requirements of the instrumentation change and as improved integrated circuits become available. A unique feature of this system is the existence of two sets of bus traces on the mother board. The second bus can be used as an extension of the system bus, an interprocessor but in a distributed processing system, a hardware driven peripheral bus, or the system bus of a second microprocessor. The second bus is shown to add substantially to the versatility and power of the system. The second bus also provides the means by which a single processor system can be upgraded into a distributed processor network without making the special interfaces designed for the single processor obsolete.

Patent
15 Jun 1984
TL;DR: In this paper, the authors consider the case where a plurality of processors are coupled to a data bus, and each of the processors contending for the data bus to output data requests each output priority byes of their transmission header packets as a series of data bits.
Abstract: In a computer network including a plurality of processors coupled to a data bus, ones of the processors contending for the data bus to output data requests each output priority byes of their transmission header packets as a series of data bits. Every contending processor sequentially reads data present on the data bus. Each processor that reads a "one" on the bus corresponding to a "zero" output by that processor interprets this as a data collision yields the bus for data transmission purposes, but continues to read all data appearing on the data bus and compares it with corresponding bits of its own transmission header packet. Only the processor having highest priority detects no data collision, and continues to output its data request. If any other contending processor determines that the data request of the highest priority processor is identical or sufficiently similar to its own, it merges its request with that of the highest priority processor by reading the resulting data, thereby reducing waiting time especially in file-intensive operations.

Patent
02 Nov 1984
TL;DR: In this article, the authors propose an approach to easily design and modify a system, by operating units connected with synchronous and asynchronous buses in relation with signals on the buses and, at the same time, making the access between optical unit connected with different buses possible.
Abstract: PURPOSE:To easily design and modify a system, by operating units connected with synchronous and asynchronous buses in relation with signals on the buses and, at the same time, making the access between optical units connected with different buses possible. CONSTITUTION:Data on the address bus 17 of synchronous buses 1 can be sent to the address bus 22 in asynchronous buses 2 through #1 driver 29 after they are temporarily held by an FF group 27. On the contrary, data on the address bus 22 of the asynchronous buses 2 can be sent to the address bus 17 of the synchronous buses 1 through #2 driver 30. Moreover, data on the data bus 18 of the synchronous buses 1 can be sent to the data bus 23 of the asynchronous buses 2 through #3 driver 31 after they are temporarily stored in another FF group 28. On the contrary, data on the data bus 23 of the asynchronous buses 2 can be sent to the data bus 18 of the synchronous buses 1 through #4 driver 32. Control of these sending routes is performed by means of signals 33-36 from a bus change-over controlling section 4.

Patent
24 Apr 1984
TL;DR: In this paper, a priority determination for the use of a data processing system where plural users gain access to parallel busses in a sequential manner based on priority determination is presented. But, the priority determination involves an allocation circuit for each user that includes a logic network comprising four bistable flip-flops, an edge triggered D flipflop and a monostable flip flop, which can be used to allow subsequent immediate access if a user wants the bus again and no other user has requested the bus.
Abstract: An allocation system for the use of a data processing system where plural user systems of the data processing system gain access to parallel busses of the data processing system in a sequential manner based on a priority determination. The priority determination involves an allocation circuit for each user that includes a logic network comprising four bistable flip-flops, an edge triggered D flip-flop and a monostable flip-flop. The flip-flop elements in conjunction with a generated request signal, bus approval signal, bus busy signal, bus claim signal, selection duration signal, compare signal, enable signal and greater or equal signal and appropriate AND, NAND, OR and inverter elements determine the winner or next user when plural user requests are received while the bus is busy. The use of the edge triggered D flip-flop allows a user subsequent immediate access if such user wants the bus again and no other user has requested the bus. The allocation system otherwise gives priority to all other entered requests before a current user if such current user has again requested the bus.

Journal ArticleDOI
TL;DR: A high-speed local area network that uses a bus architecture and spread spectrum techniques to overcome the problems of contention in a system with distributed control is described.
Abstract: A high-speed local area network that uses a bus architecture and spread spectrum techniques to overcome the problems of contention in a system with distributed control is described. Each node uses a pseudo-random binary code to modulate the data to be transmitted, effectively 'spreading' the bandwidth of the signal, and may transmit independently without first sensing the media. Interference between simultaneous transmissions is avoided by the careful selection of the codes used. The paper presents a technical description of the system developed and compares its performance with other bus networks. The choice of codes to be used, and their effect on the maximum number of nodes allowed and the data rate is discussed. The performance of the system in a noisy environment is also considered.

01 Jan 1984
TL;DR: In the trial areas, where stage carriage bus services were deregulated, were designated in parts of Norfolk, Herford and Worcester, and Devon, following the Transport Act 1980 as mentioned in this paper.
Abstract: Trial areas, where stage carriage bus services were deregulated, were designated in parts of Norfolk, Herford and Worcester, and Devon, following the Transport Act 1980. All three areas were mainly rural, Hereford being the largest town in any of them. Hereford and Worcester county council adopted a new revenue support policy, awarding contracts for subsidised bus services by competitive tender. This resulted in a transfer of services between operators, with a substantial saving in total revenue support, but little overall change in the rural bus network. There was considerable competition between unsubsidised services, mainly in Hereford but also on some inter-urban routes, with dramatic fare reductions, frequency increases and continual service changes. In the other counties revenue support policies were unaltered, and councils looked to operators to take initiatives in developing new services. The resulting changes in Norfolk and Devon were on a very small scale, and insufficient to prevent a slow overall rate of decline in rural bus services. In itself, deregulation of bus services appears to have had little effect in rural areas, but is has led to lower fares and more frequent services in the town of Hereford and on some inter-urban routes. This competition appears to be unstable, and it is not yet clear what its long-term effects may be. (Author/TRRL)

Patent
29 May 1984
TL;DR: In this article, a monolithically integratable transmission system for binary information has at least one address source which is connected to one address sink via an address bus, and the address sink is respectively allocated to a register means connected to a data bus.
Abstract: A monolithically integratable transmission system for binary information has at least one address source which is connected to at least one address sink via an address bus. The address sink is respectively allocated to a register means connected to a data bus. A clock generator generates a first clock signal and a non-overlapping, phase-shifted second clock signal. The address bus and the data bus are precharged during the first clock signal and access of an addressed register means to the data bus occurs during the second clock signal. In the time span between the two clock signals, the address bus is charged with the address signals by discharging.

Patent
26 Sep 1984
TL;DR: In this paper, an interface scheme is described which allows relatively convenient interconnection of, and re-configuration of, circuits for performing operations to digital signals from a bus, and a parallel bus (102), eight bits wide, having 320 channels per frame is provided.
Abstract: © An interface scheme is described which allows relatively convenient interconnection of, and re-configuration of, circuits for performing operations to digital signals from a bus. In one exemplary embodiment, a parallel bus (102), eight bits wide, having 320 channels per frame is provided. For each circuit (119) to be connected to the parallel bus a connection memory (106) and an input/output buffer (103) is provided to control the accessing of the parallel bus by each circuit.