Showing papers on "Bus network published in 1985"

Reliable Loop Topologies for Large Local Computer Networks

Abstract: Single-loop networks tend to become unreliable when the number of nodes in the network becomes large. Reliability can be improved using double loops. In this paper a highly reliable and efficient double-loop network architecture is proposed and analyzed. This network is based on forward loop backward hop topology, with a loop in the forward direction connecting all the neighboring nodes, and a backward loop connecting nodes that are separated by a distance ⌊√N⌋where N is the number of nodes in the network. It is shown that this topology is optimal, among this class of double-loop networks, in terms of diameter, average hop distance, processing overhead, delay, throughput, and reliability. The paper includes derivation of closed form expressions for diameter and average hop distance, throughput, and number of distinct routes between two farthest nodes. For fault-tolerance study, the effect of node and link failures on the performance of the network is analyzed. A simple distributed routing algorithm for reliable loop network operation is also presented.

Multicomputer digital processing system

Abstract: A multiple computer digital processing system including several Local Buses positioned orthogonally to a Common Bus. Each Local Bus is connected to the Common Bus through a plugably connected Common Bus interface card to provide a transfer of information between Local Buses across the Common Bus. Computer cards, memory cards and other device cards may be plugably connected to the Local Bus to communicate with each other via the Local Buses and Common Bus. The number and types of cards connected and even the number of Local Buses connected to the Common Bus may be varied according to the requirements of each application. Additionally, the Common Bus includes a shared memory accessible by all devices and an InterComputer Interrupt circuit providing interrupts to the computer cards. Further the computer cards are plugably connectable to a Peripheral Bus to provide communications with peripheral devices located externally to the system. All cards connected to the Local Buses and Common Bus include monitor circuits connected through a Test Bus to a System Monitor that configures the system according to the cards connected and the application requirements, detects errors, monitors performance, and provides fault tolerant repair capability under operator supervision.

Time multiplexed bus matrix switching system

Abstract: Ports including at least input and output signal lines are collected into port groups. For each port group three separate clock synchronized time division switches are connected respectively to the input signal lines, bus highways and the output signal lines. All time division switches of the system are synchronized by a system clock and each one is controlled by its own storage of selected addresses in time slot order. A plurality of bus highways is provided and the input time division switch connects signals to a specific bus highway of the system. A second time division switch selects the bus highway for connection to the output section of the port group. A third time division switch selects the output port to which the selected bus highway is connected. In one embodiment the bus highways directly connect the port groups. In another, a central inter-connect matrix is provided to make the connection between the first and second time division switches.

Fault-Tolerant Multiprocessor Link and Bus Network Architectures

Abstract: This paper presents a general class of regular networks which provide optimal (near-optimal) fault tolerance.

In-house distribution facility for a broadband communication system

Abstract: An in-house distribution facility has an interface unit (1) which provides a connection to the broadband communication network (2, 3). Between the interface unit (1) and the subscriber terminals (6, ..., 11), e.g., television sets, video recorders, stereophonic radio receivers, video and audio signals are transmitted over a broadband line (20). The interface unit (1) is connected to the subscriber terminals by means of an in-house communication bus (14) to which central remote control units (16) provided in the various rooms are connected via one bus adapter (15) each. The communication bus (14) has a control circuit (17) which controls the communication on this bus so that collisions are avoided. The remote control units (16) can also control subscriber terminals located in other rooms and interrogate them for their status. Moreover, signalling data for channel selection can be transmitted to the communication network. Evaluation of reflected control signals is avoided.

Peripheral controller for coupling data buses having different protocol and transfer rates

Abstract: A peripheral controller is provided for controlling data transfers between peripheral devices operably on one type of data bus to devices operable on a second data bus. An intermediate buffer is utilized so that data is read into one memory block from the sending data bus and read out of another memory block to the receiving data bus. Controls are provided to prevent overwriting data which has not been transmitted and to prevent data transfers from the buffer until at least one block of memory has been filed.

Single instruction multiple data (SIMD) cellular array processing apparatus employing a common bus where a first number of bits manifest a first bus portion and a second number of bits manifest a second bus portion

Abstract: In a cellular array including a matrixed array of processing elements, the processing elements are controlled by software to overcome manufacturing defects, to cooperate together to form words of varying size and to replace cells that become defective during the lifetime of the processor. These cells communicate with memory external to the chip via a time division multiplex bus. The bus is 32-bits wide and each cell is connected to both the upper half and the lower half of the bus. Configuration bits that are loaded into a cell cause communication over the top half or the bottom half of the bus according to the significance of the bits placed in the cells. Words between 16-bits and 246-bits in length may be formed in a case where 20 such cells are implemented on a single chip with four of the cells being deemed to be spare parts. For simplicity, typical word sizes would be 2n×16 bits although in principle any multiple of 16-bits may be obtained. Each cell contains a 16-bit multiport RAM providing general purpose registers for use by the programmer as well as systems registers. The systems registers accommodate the processor status word, a multiplier quotient register, a full-function arithmetic logic unit and path logic to connect the cells together and control the flow of information through the path logic according to the instruction being executed.

System and method for controlling network bus communications for input-output interlocking information among distributed programmable controllers

Abstract: A control system for controlling an industrial process includes a network of a plurality of distributed programmable controllers or nodes coupled serially to a communications bus on either a single or dual media by means of a shielded twisted wire pair cable. The programmable controllers are coupled to the bus through a communications module which uses a broadcast method to achieve peer-to-peer communications. One module of the network, designated as an active monitor, exercises exclusive supervisory control of the broadcast activity on the network. The active monitor polls each node coupled to the network and each active node responds by broadcasting unacknowledged data to all nodes in the network. The broadcast message of each node in the network is mapped directly into designated variable memory locations of each programmable controller on the network. The active monitor establishes a list of active nodes based on the responses to the poll and allocates a time slot to each active node to broadcast its data and on a cyclical basis continues to poll a different node each network scan to update the list. Fault tolerance is provided by either an active-passive monitor arrangement for the single medium embodiment or by a redundant medium connection for the dual media embodiment.

Multiprocessor system with standby function

Abstract: A multiprocessor system is comprised of a bus and a plurality of processor modules. Each processor module includes a bus arbitration block, a bus access control block, an address output block, a data input/output block, a clock signal generating block, a stop request block for requesting the stop of supplying a clock signal, an operation processing block for processing data, and a stop control block. The stop control block stores the contents of the bus access (a type of the bus, the address and data concerning the access, etc.) as is made by the operation processing block when the clock signal is stopped, and to what clock of that access cycle the bus access proceeds. The stop control block controls the bus arbitration block to electrically disconnect the processor module from the bus. After the restart of supplying the clock signal, the bus arbitration block, the bus access control block, the address output block and the data input/output block are restored on the basis of the contents of the bus access. Then the bus access that was stopped is resumed from its beginning. When the number of clocks of the clock signal is equal to that stored in the memory block after the restart of supplying the clock signal, the stop control block supplies again the clock signal to the operation processing block. Subsequently, the operation processing block continues the bus access.

Multiple path multiplexed host to network data communication system

Abstract: A data transfer controller allows data to be transferred from a network bus to a system bus in a host computer. The controller has a network bus interface for communicating with the network bus and a system bus interface for communicating with the system bus. The system bus interface has first and second buffers. A dual port memory is utilized and has one port operatively connected to one of the buffers in the system bus interface and to a microprocessor. The direct access channel is established and operatively connected to the other buffer of the system bus interface as well as coupled to the microprocessor and associated control logic. A switch under control of the control logic establishes connections between the second port of the dual port memory and either the direct access channel or the network bus interface.

Interface comprising message and protocol processors for interfacing digital data with a bus network

Abstract: A network interface equipment for a bus network employs separate processors and random-access memories for handling bus-protocol and data portions of a data packet. Each processor has access to a separate random-access memory to and from which it moves data. The random-access memories are multiple-ported to permit access by more than one requester with a logic arbitrator to resolve conflicts. A status random-access memory provides communication between the two processors.

Method and apparatus for bus arbitration in a data processing system

Abstract: In a bus-oriented computer system, the decision as to which unit is to receive the bus takes account of the current status of the bus system and the respective operation to be performed on the bus. For that purpose, status information of the connected units, the bus command to be executed and the address of the requested unit are fed to the allocation logic (arbiter) on separate or commonly used lines, thus avoiding idle times during the use of the bus. By evaluating the bus command, the allocation priority can be dynamically changes in order to suppress bus accesses that are bound to fail from the start.

Method and arrangement for transmitting data, especially in an aircraft

Abstract: A method and arrangement for the transmission of data, in digital form, in a bus system, which includes a central unit, several stations, as well as a bus line or data bus. During operation, the following different transmission phases take place: An initiation phase, in which the central control unit queries all of the stations and prepares a request phase; the request phase, in which the individual stations report a required bus access; an allocation phase, in which each station obtains a time slot in response to its request; and a data phase, for transmission of the data. The central unit includes a phase control, a request collector, a time slot allocator, and a register. A number of the stations are provided with a request generator in such a way that the latter can signal a need to the bus access. Thus, an optimum utilization of the transmission capacity is achieved, possibly by switching stations off. However, a rapid bus access is possible at any time for important stations.

Serial link communications protocol

Abstract: A transmission-economized serial bus protocol comprising at least one eight-bit word further comprising at least an operation code and a subargument (Fig. 2). The operation code and subargument comprise, respectively, either a start-of-message character or a start-of-reply character and either a device destination address or the device's source addresse (Fig. 3). Further, an error detection device is provided comprising an even parity bit. Moreover, there is provided an optimized method of bus contention comprising monitoring the bus (230) for an idle or busy bus condition and either attempting an asynchronous bus access if the bus is idle or synchronously attempting a prioritized retry after a busy bus condition is sensed, after a bus access collision is sensed, and upon initial power-up, synchronized to the current message completion. The prioritization comprises a constant time delay plus a bit-time delay proportional to an accessing device's address identification (Fig. 5). Finally, there is provided an optimized method of inter-device (120, 140, 150, 180, 190, 200) message addressing and handshaking in a multi-access, bussed system, each device having a source and destination address, comprising addressing a message to a destination address and awaiting the addressed destination device to acknowledge by echoing its corresponding source address and also monitoring the bus (230) for an announcement of a source addressed event and performing a function accordingly.

Occupancy control system for plural serial buses

Abstract: Plural stations are connected to two independent serial buses and they are permitted to occupy a first serial bus in a predetermined order under control of a bus controller. A second serial bus is used for transmitting to the bus controller an urgent bus occupancy request issued by any of the stations. Upon receipt of the urgent bus occupancy request, the bus controller permits the request-issuing station to occupy the first serial bus regardless of the predetermined order, thereby insuring a fault-free operation of the system for transmitting data between the stations.

Digital timeslot and signaling bus in a digital PBX switch

Abstract: A switch in a digital PBX system supporting both centralized and distributed switching techniques. The switch has nearly universal parallel bus (10) between line card modules. The bus having a timeslot bus capable of having more than one line card module connected to it, which may communicate voice PCM or data signals during one timeslot. The bus (10) also has a signalling bus (26, 27, 28, 29) by which line card modules are selected to communicate with a central control module by a single line to maintain the universality of the bus (10). Signalling information is also passed between a selected line card module and the central control module by a pair of parallel lines (27, 28).

Distributed bus arbitration for a multiprocessor system

Abstract: A computer system has a plurality of processors sharing a bus. Bus arbitration circuitry is located on each processor for determining bus access. The identity of the processor which is responsible for arbitrating bus access changes from time to time. Each processor has a plurality of possible arbitration states, which are controllable through execution of software by the processor.

Serial bus system and method for selection of bus subscribers

Abstract: In a serial bus system an active representation of the logic states of a bus signal for transmission of both logic states is implemented either on two separate lines for separate transmission of the logic states thereon or on a single line with both logic states being represented by different frequencies. In the method selection of a subscriber connected to the bus, the subscribers wishing to transmit a message indicate this by issuing a collision signal to the bus. The time period during which the collision signal is issued by each subscriber is chosen in such a way that each subscriber of the bus has the possibility to be prepared for the selection. The selection of the subscriber wishing to transmit a message then is done by means of an address comparison on a bit-by-bit basis.

Processor access control arrangement in a multiprocessor system

Abstract: In a multiprocessor system, processors are connected to an interconnecting bus by means of bus interface circuits which comprise an address buffer in addition to data buffers. The interconnecting bus, in addition to a destination address and data also carries an originating address identifying the processor transmitting the data. In the event of a receive buffer overload condition in the receiving bus interface circuit, a negative acknowledge signal is transmitted on the bus and the originating address is queued in the address buffer. When the buffer overflow condition has been relieved, a retransmission request is sent to the first processor identified in the address buffer and its message is received. This procedure will be repeated for each processor identified in the address buffer.

Program controlled bus arbitration for a distributed array processing system

Abstract: © A distributed array processing system includes a bus divided into two portions or segments by a switch. One segment is connected to a processor and to a bus arbiter for controlling use of the bus. The bus arbiter provides one source of bus grant signals. A control register provides a second source of bus grant signals and additional signals for disabling the arbiter and actuating the switch. The control register is software controlled, i.e., it is loadable with data or control signals, under program control, to control use of the bus.

Digital carrier channel bus interface module for a multiplexer having a cross-connect bus system

Abstract: A digital carrier channel bus interface module is disclosed for a multiplexer having a cross-connect bus system. Random access memory is loaded or unloaded by a serial-to-parallel or parallel-to-serial converter respectively with data in parallel format off a digital carrier line. A high speed digital carrier module controls high speed data transmission over the bus system to another digital carrier channel. Receive and transmit addresses are sequentially routed over receive and transmit address bus lines of the bus system so that bus drivers and bus receivers of the channel bus interface module may appropriately actuate the routing of data in parallel over the bus system.

Technique for dynamic resource allocation in a communication system

Abstract: The present invention relates to a dynamic resource allocation technique for multiple users of a channel that employs variable coding and associated redundancy to provide a maximum data rate for various demand conditions while simultaneously providing a maximal margin that is matched to the current demand condition. For such technique, each first data rate input signal is synchronized to a second higher data rate, the synchronized signals are then separately demultiplexed for propagation along separate paths and encoded in a separate variable rate coder (VRC). The output from each VRC is stored in a separate bus interface which contends for a common bus when full. A rate controller maintains the activity on the common bus at a minimum level by either monitoring (1) the activity on the bus, (2) the rate the bus interfaces are filling up, or (3) both (1) and (2) above, and in response thereto to transmit control signal to the VRCs to appropriately vary the codes and redundancy used.

Bus to bus converter using a RAM for multiple address mapping

Abstract: An improvement in a bus converter that provides a bus to bus address translation function permitting access from an I/O device connected on the I/O bus to a system bus and system memory, where the bus converter includes a circuit connected to the I/O bus to partition I/O addresses received from the I/O bus into a lower order field and a high order field and connected to a circuit to receive DMA ID's from the I/O bus to combine this DMA ID with the high order field to form a first combined address. The first combined address is input to a memory which provides corresponding control field and prefix field data. An address formatter is further included that is connected to receive the control field and prefix field data from the memory and further connected to receive the low order address field. The address formatter forms a second combined address from the prefix field, control field and lower order address field. This second combined address is then provided to a system bus to permit access to the system bus.

Apparatus for maximizing bus utilization

Abstract: An interactive terminal computer system is disclosed having a system bus for communicating between elements of the computer system which has apparatus for permitting the execution of a maximum number of concurrent bus cycles without interference with each other.

Switch apparatus for a video interconnection system

Abstract: A video component interconnection system includes a single signal conductor video bus serially coupled between each of the video components for conducting video signal between the components. A switch located in series with the video bus separates the continuity of the video bus when it is non-conductive. A shunt switch arrangement coupled to the video bus at its junction with the series switch, applies an impedance substantially equal to the characteristic impedance of the video bus between the video bus and a reference potential, when the series switch separates the continuity of the video bus, in order to reduce ghost-producing reflections.

Microcomputer with a bus accessible from an external apparatus

Abstract: A microcomputer provided with a direct memory access (DMA) controller comprises a central processing unit (CPU), which includes a CPU timing controller, an address computation section, and an address bus output buffer coupled between the output of the address computation section and an external address bus. The CPU also includes an auxiliary timing controller operative, in response to a hold request from a DMA controller, to output a HOLD acknowledge (HOLDA) signal to the DMA controller and to reset a BUS ENABLE signal to the address bus output buffer, so tha the CPU is isolated from the external address bus. The CPU further includes an address latch circuit connected between the output of the address computation section and the address bus output buffer to temporarily hold the address output in response to a latch signal from the auxiliary timing controller, so that the address output is supplied to the address bus immediately when the latch signal is reset at the termination of the DMA operation.

A Reconfigurable High-Speed Optical System for Integrated Local Communications

Abstract: The introduction of optical fibers in local area networks makes it possible to implement wide-band communication systems integrating all the communication services (telephone, data, images, etc.) foreseen in future office scenarios. This paper describes a reconfigurable high-speed local communication system, which is currently under development at the Centro Studi e Laboratori Telecomunicazioni (CSELT), conceived to attain high reliability and efficiency features, therefore suitable for a wide range of application environments, such as automated offices, integrated manufacturing, hospitals, etc. The access organization is based on a hybrid (i.e., circuit and packet) protocol, which guarantees each type of traffic the required grade of service, while allowing an optimal exploitation of the transmission capacity. Fault-tolerance issues are taken as a guideline in the overall system conception and, in particular, in the transmission subsystem design. The transmission subsystem presently uses available optical technology to implement a loop-shaped bus topology capable of reconfiguring by means of a distributed algorithms, when a link or node fails.

Circuit arrangement for centrally-controlled telecommunications exchange systems, comprising central control units and an alternate circuit arrangement

Abstract: Two parallel-operated control units each communicate via a respective discrete bus with a respective assigned group of switch devices, and given an alternate circuit based on one control unit simultaneously accepting the tasks for both groups, an alternate circuit bus is provided from the accepting control unit to the other group of switch devices and has bidirectional bus amplifiers connected therein, the one bus amplifier being supplied with voltage together with the accepting control unit and its group and the other bus amplifier being supplied with voltage together with the other control unit and its group. Given a voltage outage of the non-accepting control unit and its assigned group of switch devices, a signal is transmitted to the first-mentioned bus amplifier in order to provide the required disconnection of the alternate circuit bus by way of unequivocal electrical switch states and measures in that bus having supply voltage present.

Regenerative simulation methods for local area computer networks

Abstract: Local area computer network simulations are inherently non-Markovian in that the underlying stochastic process cannot be modeled as a Markov chain with countable state space. We restrict attention to local network simulations whose underlying stochastic process can be represented as a generalized semi-Markov process (GSMP). Using "new better than used" distributional assumptions and sample path properties of the GSMP, we provide a "geometric trials" criterion for recurrence in this setting. We also provide conditions which ensure that a GSMP is a regenerative process and that the expected time between regeneration points is finite. Steady-state estimation procedures for ring and bus network simulations follow from these results.

Automatic rerouting of calls through data buses

Abstract: A redundant (multiple) bus system for interconnecting a plurality of data source and destination entities and arranged to direct data communications over an alternative bus in the event that a prior call to a destination over a first bus was unsuccessful. Each source entity maintains a table designating a separate logical path over each bus to each destination entity, marking each path designation in accordance with the success or failure of calls directed through the path. The bus selection for delivering a communication to any destination is determined in accordance with designation markings for the paths to the destination and independent of designation markings for paths to other destinations whereby a bus may be selected for a delivery to one destination even though prior deliveries over the bus to other destinations have failed.