Showing papers on "Bus network published in 1986"

Bus network design

Abstract: This paper describes the bus network design problem, summarizes the different approaches that have been proposed for its solution and proposes a new approach incorporating some of the positive aspects of prior work. The proposed approach is intended to be easier to implement and less demanding in terms of both data requirements and analytical sophistication than previous methods. An algorithm is presented that can be used to design new bus routes taking account of both passenger and operator interests; however, this algorithm focuses on only a single component of the overall bus operations planning process described in this paper.

The Fastest Path through a Network with Random Time-Dependent Travel Times

Abstract: This paper introduces the problem of finding the least expected travel time path between two nodes in a network with travel times that are both random and time-dependent (e.g., a truck, rail, air or bus network). It first shows that standard shortest path algorithms (such as the Dijkstra algorithm) do not find the minimum expected travel time path on such a network, then proposes a method which does find the minimum path. Next, this paper shows that the optimal “route choice” is not a simple path but an adaptive decision rule. The best route from any given node to the final destination depends on the arrival time at that node. Because the arrival time is not known before departing the origin, a better route can be selected by deferring the final choice until later nodes are reached. A method for finding the optimal adaptive decision rule is proposed.

Circuit arrangement for testing a passive bus network with the carrier sense multiple access with collisions detection method

Abstract: A circuit arrangement is provided for testing a passive bus network system which comprises stations which are connectible to a coaxial cable segment via media adapter units, the stations realizing the data packet exchange via the coaxial cable segment with carrier sense multiple access with collision detection access method. In conjunction with a status receiving device which monitors the transmitted data packets, the passive bus network system is monitored by the data transmitter and the data receiver in view of the presence of the line terminating impedances, the proper connection of the media adapter units to the transmission medium, as well as the transmitting and receiving functions and the collision recognition and state of the collision recognition circuit.

Bus device for use in a computer system having a synchronous bus

Abstract: A bus device is provided for use in a data processing system which includes a plurality of bus devices interconnected by a synchronous bus. The bus includes multiplexed data/address/arbitration lines which carry data, address, and arbitration information during respective data, command/address, and arbitration cycles. The bus also includes a BUSY line and a NO ARB line for controlling access to the data/address/arbitration lines. Where constructed as a memory device, the bus device includes memory circuits having a plurality of storage locations, and an interconnecting circuit which monitors the BUSY and NO ARB lines to identify various types of cycles on the bus, and which controls transmission of signals from the memory device over the bus in accordance with information derived by the monitoring means from the BUSY and NO ARB lines.

Digital data processor apparatus with pipelined fault tolerant bus protocol

Abstract: A fault-tolerant computer system provides information transfers between the units of a computing module, including a processor unit and a memory unit and one or more peripheral control units, on a bus structure common to all the units. Information-handling parts of the system, both in the bus structure and in each unit, can have a duplicate partner. Error detectors check the operation of the bus structure and of each system unit to provide information transfers only on fault-free bus conductors and between fault-free units. The computer system can operate in this manner essentially without interruption in the event of faults by using only fault-free conductors and functional units. Arbitration circuits of unusual speed and simplicity provide units of the computing module with access to the common bus structure according to the priority of each unit. The units of a module check incoming and outgoing signals for errors, signal other module units of a detected error, and disable the unit from sending potentially erroneous information onto the bus structure.

Serial data bus for serial communication interface (SCI), serial peripheral interface (SPI) and buffered SPI modes of operation

Abstract: The aim of the Chrysler Collision Detector (CCD) Bus System is to allow multiple microprocessors to easily communicate with each other over a common pair of wires (called a bus) using a scheme similar to a telephone party line. All microprocessors connected to the bus are able to receive all messages transmitted on the bus. Any microprocessor with a message to transmit on the bus waits until any current user is finished before attempting to use it. Whenever the bus is available, its use is allocated on a first-come, first serve basis (i.e., whichever microprocessor first begins transmitting its message on the bus after any previous message finishes gets the use of the bus). If, however, multiple microprocessors attempt to begin transmitting their messages on the bus at exactly the same time, then the message with the highest priority wins the use of the bus. All messages have unique message priority values and each message is transmitted by only one microprocessor. The subject invention provides the ability to communicate with a SCI port, a SPI port or a buffered SPI port. This allows communication with any device configured with any one of these ports, all on the same bus.

Method of data arbitration and collision detection in a data bus

Abstract: A method of blocking data transmission from a user microprocessor to a data bus utilizing arbitration and collision detection in a data bus interface integrated circuit utilizing a Serial Communication Interface (SCI) port on the user microprocessor.

Microprocessor with integrated CPU, RAM, timer, and bus arbiter for data communications systems

Abstract: A microprocessor device used as an adapter for a communications loop of the closed-ring, token-passing, local area network type is disclosed. Each station on the ring has a host processor with a host CPU, a main memory, and a system bus. The microprocessor device therein which operates relatively independently from the host CPU, and which is coupled to the main memory by the system bus, includes a local CPU, a local read/write memory, an on-chip timer, a local bus and a bus arbiter. A transmit/receive controller is connected between the ring and the microprocessor device. This controller is coupled to the local bus to directly access the local read/write memory, also under control of the bus arbiter. The local CPU executes instructions fetched from a ROM accessed by the local bus, so the local CPU instruction fetch, the direct memory access from the transmit/receive controller for transmitting or receiving data frames, and the access from the host CPU for copying transmitted or received message frames, all contend for the local bus. Bus arbitration with appropriate priorities is used to control access to the local bus. The on-chip timer accessed by the local bus provides the time period used to monitor and control the communications protocol.

Method for communicating data on a communication network by token passing

Abstract: A method of determining access on an electronic serial bus by implicit token passing. The serial bus receives and transmits data between a plurality of devices. Each device has a receiver for receiving data to the serial bus, a transmitter for transmitting data to the serial bus, a bus idle timer for detecting an idle condition on the bus, and a bus access timer for controlling access to the serial bus. Each device is assigned a unique bus address. The bus access timer of each device is loaded with a value representative of each device's own unique bus address and the unique bus address of the transmitting device. The bus access timer starts a count upon receiving an end of transmission condition from the transmitting device and stops upon receiving a start of transmission condition from the transmitting device. When a bus access timer of a device reaches a predetermined value, the device of the timed out bus access timer is given access to the bus.

Method and apparatus for bus arbitration using a pseudo-random sequence

Abstract: The present invention discloses a second level bus arbitration method and apparatus for use with a distributed computer network. The invention alleviates any simultaneous access possibility by requiring any computing element which claims access to the bus to first send a pseudo-random sequence over a common line using open collector logic. A computing element can access the bus if the sequence appearing on the common line is the sequence it transmitted. The invented arbitration system does not require central control or centralized clocking.

I/O structure for information processing system

Abstract: An I/O structure for use in a digital data processing system of the type in which system components including a processor and a system memory are connected by a system bus. The I/O structure includes a system bus interface connected to the system bus, a synchronous satellite processing unit (SPU) bus connected to the system bus interface, one or more satellite processing units (SPUs) connected to the SPU bus, and peripheral devices attached to the satellite processing units. Each SPU has three main components: control logic including a microprocessor for controlling the SPU, a device adapter specific to the peripheral device for controlling the peripheral device and transferring data between the peripheral device and the SPU, and an interface unit connected to the control logic and the device adapter for providing I/O communications to the SPU bus and responding to I/O communications on the SPU bus. The I/O communications fall into two classes: communications to SPUs and communications to system components. The communications to SPUs all require a single SPU bus cycle; the communications to system components require one or more cycles. The system bus interface translates communications to system components into communications on the system bus and translates communications on the system bus intended for a SPU into communications to SPUs. The SPU bus includes first lines for carrying an I/O command and an identifier for an SPU involved in the communication and second lines for carrying the contents of the communication. In multicycle communications, the I/O command and identifier remain on the first lines for all cycles, but the information on the second lines varies from cycle to cycle.

CSMA-CD with channel capture

Abstract: This invention relates to an efficient CSMA/CD-based protocol for a local area network using an unidirectional global bus architecture, in which a ready station captures the bus for one packet time only if no other stations to its left transmit along with it. A modified version of the protocol provides a fairer access to the bus. This new scheme is a variable priority structure in which each station has a priority that changes dynamically with the state of the system. This is a contention scheme that behaves like a generalized and very flexible reservation protocol. A performance analysis of both versions of the protocol results in channel efficiency and transmission delay figures that are superior to those of the leading bus protocols.

Serial data bus for intermodule data communications

Abstract: A bus interface integrated circuit is presented which utilizes an arbitration detector, a collision detector and a contention permitting differential transceiver to work with a serial communication interface port on a microprocessor to determine between contending messages which message gains access to the communication bus by using the value or priority of the ID byte without losing bus time.

Communication bus interface

Abstract: A communication interface for controlling the transfer of data between a host processor configured to process data of a first length and a remote storage member configured to store data of a second length includes a bus controller for transferring data between the interface and the remote storage member, a data transfer member for controlling the transfer of data between the host processor and the interface, and a control processor for controlling operating of the bus controller and the transfer member. A first storage member stores data words of said second length and sequentially outputs the data words over a communication bus to the host processor configured to transmit data words of said first length. A second storage member stores data representing the operating status of the transfer member and the bus controller, enabling the control processor to monitor the status of the transfer member and the bus controller.

Method for implementing a token passing ring network on a bus network

Abstract: A method is disclosed for implementing a token ring network on a token bus network. In accordance with the invention a token ring node is connected to each one of a plurality of token bus nodes such that the token ring node appears to the token bus node to which it is connected as station equipment and the token bus node appears to the token ring node as both the next token ring node and the preceeding token ring node in a ring network. A message is transmitted from a token ring node by forming a token ring frame and transmitting the token ring frame to the next token ring node which is the token bus node to which the token ring node is connected. The token bus node encapsulates the token ring frame that it receives in a token bus frame and transmits the resulting token bus frame to a destination bus node. The destination bus node receives the token bus frame, removes the token ring frame that is encapsulated therein and forwards the token ring frame to the token ring node connected to the destination bus node.

Packet bus interface

Abstract: The Arbitrated Bus Interface (ABI) is a set of custom LSI circuits which sends and receives minipackets of binary information to and from a data bus. The ABI performs arbitration, address recognition, and buffering required for transmitting and receiving mini-packets of information between the local packet bus and a microprocessor.

Selective voltage supply system for data network distributor

Abstract: In a data network distributor adapted to connect a plurality of data stations with each other directly, and with remote stations over a network bus, a selective voltage supply system allows units shared in common with the local data stations to be powered only as needed, and to draw power from the individual data stations requiring service. Individual power sources in each data station are connected to a common line through decoupling diodes and current limiting resistors, and the common line supplies a plurality of voltage supply units which are operative to supply power to commonly used units as needed, including transmitting and receiving units for the network bus, a data diversion device for diverting local communications from the network bus, and a common control circuit for data collision recognition.

Versatile interconnection bus

Abstract: A bus arbitration system comprising a plurality of bus lines and a clock which produces first and second phrases in which a drive generates a first logic state during the first phase to precharge the capacitance associated with the bus lines and generates either first or second logic state during the second phase. Also, a bus interface is described in which different types of information are transmitted during different phases.

Search technique for identifying slave devices connected to a serial bus

Abstract: A slave device detecting system utilizes the past history of devices connected to a data bus to optimize the time required to re-establish communications. Whenever a master controller senses a condition that requires an assessment of devices on the bus, it examines the addresses of previously connected devices at more frequent time intervals than it does for addresses that were not previously associated with connected devices. In a preferred approach, all valid addresses can be examined in a sequential fashion, and the address of the previously connected device can be examined at every fifth or tenth position in the sequence. With such a technique, a device will be detected much faster once it has returned to the bus.

A reconfigurable high-speed integrated local network

Abstract: The local network comprises a plurality of active nodes (N1 . . . Nn) placed along a folded unidirectional bus (1) which presents a writing branch (1W) and a reading branch (1R). The nodes present means (RR) for network reconfiguration in the presence of a failure, through an isolation of the parts concerned by the failure, through an isolation of the parts concerned by the failure, and for regular service restoration after the repair, and means (GA) for the implementation of an ordered access protocol, which is based on the physical position of the nodes (N1 . . . Nn) and allows hybrid frames to be transmitted through the bus (FIG. 1).

Local area network operating on the multiple bus system

Abstract: A local area network operates on the multiple bus system and with a plurality of interface modules connected between the multiple bus system and data-processing/generating subsystems. Each interface module is provided with several autonomously operating bus adapters connected to separate lines of the multiple bus system including locally controlled buffer memory means. Each interface module is further provided with a local distribution circuit connected to the buffer memory means of the interface module and to a host interface unit for the subsystem to be connected to the interface module.

Lan controller having split bus design

Abstract: A split bus architecture which separates the processor/processors and the procedure memory coupled to a microprocessor (μP) bus from all direct memory access (DMA) devices coupled to a DMA bus. A coupler mechanism provides bus isolation of the microprocessor bus from the DMA bus and permits the processor to access devices on the DMA side when addressed. This separation allows data transfers to proceed on one side of the bus without interfereing with software execution on the other side of the bus.

A transmit-secure non-blocking circuit-switched local area network

Abstract: A switching system or local area network is non-blocking, transmit-secure and employs a star type topology. A back plane uses n(n-1) bus lines to interconnect n ports. Each port can transmit on any one of n-1 bus lines depending on the identity of the destination port. Likewise, each port can receive from any of n-1 bus lines, depending on the identity of the transmitting port. Signalling as well as data flow on the same bus lines. Each of the ports includes a dedicated microprocessor along with an arbitrator to resolve contention. The ports further have transmit and receive multiplexers coupled between the back plane and an associated work station or information source/sink.

Computer system comprising a data, address and control signal bus which comprises a left bus and a right bus

Abstract: A computer system comprises a bus for data, address and control signals which is divided into a left bus and a right bus by a first gating device. The gating device has an open state which is character-wise activated by a right bus request transported on the left bus. Furthermore, the gating device conducts start signals from a processor station connected to the left bus and interrupt signals from a peripheral apparatus connected to the right bus. In the closed state of the gating device, bulk data transport is possible on the right bus without interfering with the processor station. The processing speed is thus increased.

DMA control device for the transmission of data between a data transmitter

Abstract: A Dynamic Memory Access (DMA) control device for transmitting data between a data transmitter and a data receiver via an external bus formed of a data bus, an address bus and a control bus, and has a multiplicity of data transmitters/receivers and at least one microprocessor connected thereto. The transmission of the data in the external bus depends upon a channel program containing channel transfer commands and channel control commands, and includes a central control unit for addressing, dependent upon a channel command, a microcommand, address and control signals corresponding to the microcommand on an internal address-control bus; an address unit is connected to the internal address/control bus and to an internal data bus wherein addresses of a data transmitter, data receiver and the channel program are stored. The address unit delivers an address and simultaneously computes and stores the delivered address; a data unit provides interim data storage; a byte counter unit is connected to the internal data bus and address/control bus for counting the number of bytes to be transmitted; a data transmitting bus interface circuit is connected to the output of the address unit, to the external address bus and to the internal address/control bus, and to the external data bus. A control register is connected to the internal bus for receiving a channel command word, status words and other control information, from which lines for transmitting control signals extend to the central control unit; the units have devices for independently executing the tasks assigned to them.

Computer bus deadlock prevention

Abstract: A digital computing system includes at least a first and a second bus with at least a first master connected to the first bus and a second master connected to the second bus. The first master is capable of requesting the second bus through the first bus and the second master is capable of requesting the first bus through the second bus. Central conversion means receives both requests and has circuitry for generating a response signal to the first bus when both requests come simultaneously. The first master receives the response signal and continues the cycle, but without continuing the request for the second bus. The cycle is completed as though the request had been completed.

Linking interface system using plural controllable bidirectional bus ports for intercommunication amoung split-bus intracommunication subsystems

Abstract: A plurality of data processor components are distributed along a plurality of intracommunication bus systems, each intracommunication bus system having an address bus and each being assigned a unique set of addresses, with at least one of the components associated with each of the intracommunication bus systems including an address signal generator for generating address signals over the address bus of the associated intracommunication bus system An intercommunication bus system is utilized in combination with a plurality of link interface units, with each link interface unit connected between the intercommunication bus system and a corresponding one of the intracommunicaton bus systems, for carrying out communication of information over the intercommunication bus system between first and second of the intracommunication bus systems, in response to the address signals on the address bus of the corresponding one of the intercommunication bus systems A related method is also provided

Telecommunications exchanges allocating variable channel bandwidth

Abstract: In a time division multiplexed digital switching system intercommunication between telephony groups is by way of a serially operated data bus (2). Allocation of bandwidth on the data bus (2) is on a needs basis under control of a common control responsive (3) to requests from either applications processors or interface modules (10,20). The interface modules (10,20) receive addressing information from the common control (5) on a serially operated control bus (1) only when a change of status of a communication at least partly affecting that module (10,20) occurs. Such changes of status include new communication set-ups, communication clear-down, bandwidth increase and bandwidth decrease. Dynamic re-allocation of bandwidth of the data bus (2) occurs without affecting communications in progress.

Level converting bus extender with subsystem selection signal decoding enabling connection to microprocessor

Abstract: The bus extender circuit is a least replaceable unit which interfaces between intermodule subsystems and the microprocessor controller of the system. The bus extender circuits are structured so that the subsystem modules may be placed in different power zones. As a result, one subsystem may be powered down without affecting the other subsystems connected to the microprocessor's bus. In addition, the bus extender circuit converts from Fairchild Advanced Schottky TTL logic to high-speed CMOS logic and vice versa and allows bus interface gate arrays located in each subsystem to interface between the subsystem logic and the microprocessor. This bus extender circuit design eliminates the need for strapping options or DIP switches for address decoding.

System and method for controlling network bus communications for tightly coupled information among distributed programmable controllers

Abstract: E) A control system for controlling an industrial process includes a network of a plurality of distributed programmable controllers or nodes coupled serially to a communications bus on either a single or dual media by means of a shielded twisted wire pair cable. The programmable controllers are coupled to the bus through a communications module which uses a broadcast method to achieve peer-to-peer communications. One module of the network, designated as an active monitor, exercises exclusive supervisory control of the broadcast activity on the network. The active monitor polls each node coupled to the network and each active node responds by broadcasting unacknowledged data to all nodes in the network. The broadcast message of each node in the network is mapped directly into designated variable memory locations of each programmable controller on the network. The active monitor establishes a list of active nodes based on the responses to the poll and allocates a time slot to each active node to broadcast its data and on a cyclical basis continues to poll a different node each network scan to update the list. Fault tolerance is provided by either an active-passive monitor arrangement for the single medium embodiment or by a redundant medium connection for the dual media embodiment.