Showing papers on "Bus network published in 1987"

Cordless accessed high-speed high-capacity local area networks

Abstract: The present invention relates to a high-speed high-capacity Local Area Network (LAN) wherein each user, of a separate group of one or more of the network users, communicates cordlessly, using radio frequencies or infrared, with an assigned Regional Bus Interface Unit (RBIU) located in the proximity of the group. Each RBIU of the network interfaces with a high-speed serial or lower speed parallel bus of an open-ring network for purposes of transmitting information signals while receiving information signals via the high-speed serial network bus (es), Various communications protocols such as, for example, CSMA/CD, slotted ALOHA, etc. can be employed by the users in communicating with the associated RBIUs with high efficiency due to the short paths involved relative to the transmission frame durations used on the bus.

Multiple Bus Architectures

Abstract: A recent study noted that for shared memory multiprocessors the single system bus typically used to connect the processor to the memory is by far the most limiting resource, and system performance can be increased considerably by increasing the capacity of the bus. One way of increasing the bus capacity, and also the system's reliability and fault tolerance, is to increase the number of buses. In this article the authors discuss using multiple buses to provide highbandwidth connections between the processors and the shared memory, thereby allowing the construction of larger and more powerful systems than currently possible.

Direct memory access apparatus and methods for transferring data between buses having different performance characteristics

Abstract: Methods and apparatus are disclosed for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit ("CPU") is attached, and a second bus, to which a second set of relatively lower performance devices is attached. More particularly the invention accomplishes the transfer function in a manner that facilitates communication between the first and second set of devices from the comparatively lower performance of the second set of devices. Direct memory access ("DMA") apparatus and methods are disclosed, including a set of direct memory access channels. The DMA channels may be used to transfer data between the high performance channel (hereinafter referred to as the "Local Bus") coupled to the CPU in a reduced instruction set computer (RISC) system and a typically lower performance, peripheral bus (hereinafter referred to as a "Remote Bus"). The resulting DMA interface between the Local Bus and a Remote Bus permits a wide performance range of standard peripheral devices to be attached to the RISC system in a manner that does not limit system performance. The noval DMA may also be used as part of a data transfer controller (DTC) having other components, such as I/O ports, or may be used independently for transferring data between unmatched buses in, for example, computer systems, data transmission systems and the like.

Multi-processor, multi-bus system with bus interface comprising FIFO register stocks for receiving and transmitting data and control information

Abstract: A multi-processor, multi-bus system comprises a host processor and a cluster controller coupled to a first type of bus; a local processor coupled to a second type of bus; and bus interface circuits coupled to the first and second bus types for selectively enabling the second bus to be coupled to the host processor, and for selectively enabling the first bus to be coupled to the local processor. Both bus types are asynchronous. Each bus interface circuit comprises a first-in-first-out (FIFO) register, interrupt logic, and transmitter/receiver logic. The pair of bus interface circuits together provide dual simplex data transfer between the local processor and the cluster controller which is directed by a parallel data ling (PDL) protocol. The protocol utilizes a 16-bit wide control word. The most significant bit 15, referred to as the command bit, is a "one" whenever bits 0-7 contain a command byte, while the command bit is "zero" whenever bits 0-7 contain a data byte. A logical unit number specified in bits 8-14 indicates to which of 128 possible logical devices the information transfer is destined.

Bus arbitration system and method

Abstract: A bus arbitration system for use in a data processing system which operates on clocked cycles for determining priorities in accessing a system memory and one or more local memories associated with processor units is shown. Each of the processor units are operatively coupled through a local bus to its associated local memory. A system bus interconnects the processor units and local memories in parallel to the local bus and the system is connected to an input/output device and the system memory. The bus arbitration system monitors requests made by processor units or the input/output device for access to the system memory or a local memory during the clock cycle. A determination section of a bus arbitration module determines whether access is available over the system data bus or a local data bus. A priority logic section identifies the existence of a conflict due to one or more of the processor units and the input/output device requesting access over the system bus to either the system memory or the same associated local memory during the clock cycle and for granting a request to a selected one of the processor units or the input/output device for accessing either the system memory or one of the associated local memories over the system bus. When a processor unit is denied access to the system bus, and in the absence of a conflict in request for the same associated local memory, a request is granted to a processor unit to access its associated local memory over its local bus during the clock cycle.

Parallel searching system having a master processor for controlling plural slave processors for independently processing respective search requests

Abstract: A parallel processing search system for searching and updating a database at the request of a host system, including a master processor connected to a host system bus for transfer of information between said master processor and the host system bus; a data bus connected to the master processor; plural slave processors connected to the data bus for independently processing search respective requests under the control of the master processor; a disk drive interface adapted to be connected to a disk which stores a database; and a buffer memory connected to the data bus and the disk drive for storing the database retrieved from the disk and for sequentially placing data from the database on the data bus for match comparison by the slave processors so that a search of the database can be made by the slave processors under the control of the master processor. The buffer memory is also capable of storing updated data obtained from the host system via the master processor so that an updated database can be transferred to the disk memory via the disk drive interface.

Lookahead bus arbitration system with override of conditional access grants by bus cycle extensions for multicycle data transfers

Abstract: A node for obtaining access to a bus. In this arbitration method, the node receives a conditional grant. The node determines whether access to the bus will actually transfer to it. The node contains distributed logic that examines an extend bus cycle signal to determine whether it can become a transmitter to transfer messages on the bus. When the node becomes a transmitter, it generates an extend bus cycle signal to maintain access to the bus when executing a multi-cycle transfer, even though other nodes, perhaps with higher priorities, require access to the bus.

Structured design method for generating a mesh power bus structure in high density layout of VLSI chips

Abstract: An automated LSI chip layout arrangement includes automated layout of the power bus distribution network. A complete interlocking mesh of buses is run in routing channels lying between groups of circuits to be powered. Each segment of the mesh powering net which affects the chip size is tested to see if it can be removed without adversely affecting the power distribution. If it can be removed, the segment is deleted. The next segment which is critical to the size of the chip is then tested, and the process is continued. Those segments of the power bus distribution network which do not affect the size of the chip are not eliminated. Thus, a low-resistance power distribution bus network is guaranteed, and chip size is minimized.

Bus controller command block processing system

Abstract: A dual-purpose integrated circuit for use in a MIL-STD-1553B bus system performs the bus-related functions of both the bus controller and of a remote terminal. The circuit incorporates a number of finite-state machines that are programmed by the host CPU to execute one or more series of message transfers with little or no intervention from the CPU.

Data flow control arrangement for local area network

Abstract: In local data distribution network configuration a plurality of bidirectional data distribution busses 110 are each connected to a bus master control circuit 129 at a terminal end of the bus. Connected to each of the data distribution busses are a plurality of passive outlets 161 to which intelligent connectors or stations 160 may be connected. Each station has a unique address and is utilized for individually coupling data processing devices 120 to the bus. Grouped pluralities of the bus master control circuits are included within a bus termination hub facility 130. Data from any of the bus master control circuits may be transferred by the bus termination hub via a data trunk 111 as part of a star type configuration, to a central switching circuit 150 such as a virtual circuit switch. Direction of data flow on each of the bidirectional busses and periodic temporary synchronization of the stations is controlled in response to signals transmitted to the bus by the bus master control circuitry associated with that bus. A bus termination hub switching facility cooperates with the included group of bus master control circuits to interconnect data processing stations on the various busses with the virtual circuit switch via the trunk line and with each other. The bus termination hub facility further includes bus monitoring, status polling and maintenance facilities. A faulty bus will be disconnected if a fault is discovered during monitoring intervals. It will remain disconnected until the fault is corrected.

Bus adapter module for interconnecting busses in a multibus computer system

Abstract: A control adapter module in a bus adapter connecting a high-speed pended bus to a slower speed non-pended bus functions as a node of the non-pended bus. An interconnect bus extends between the control module and a response adapter module functioning as a node on the pended bus. Control signals on the interconnect bus generated by the response module comprise status signals having an indefinite assertion duration, and are deasserted only in response to control signals on the interconnect bus generated by the control module, which have a finite duration. Control signals on the interconnect bus generated by the response module are synchronized by a dual-rank synchronizer controlled by two phases of a multiphase clock signal derived from the clock signal of the non-pended bus. Control signals on the interconnect bus generated by the control module are synchronized by a dual-rank synchronizer controlled by two phases of a multiphase clock signal derived from the pended bus clock signal.

Bus arbitration network capable of quickly carrying out arbitration among bus masters

Abstract: In a bus arbitration network comprising a common bus network, a plurality of bus masters, and a bus arbiter, each of the bus masters supplies others of the bus masters through the common bus network with either a normal bus request signal or a particular bus request signal having a high priority in comparison with the normal bus request signal. A bus request signal is also supplied from each bus master to the bus arbiter which delivers a bus acknowledgement signal to each bus master. Supply of either the normal or the particular bus request signal and the bus request signal is prohibited by each bus master when each bus master is supplied with the particular bus request signal from the other bus masters. A lock signal may be delivered from each bus master to the other bus masters through the common bus network to continuously use the common bus network. Reception of such a lock signal in each bus master results in interruption of production of either the normal or the particular bus request signal and the bus request signal.

High speed synchronous/asynchronous local bus and data transfer method

Abstract: A high speed local synchronous bus is disclosed for coupling processors within a multi-processor system such that local memory and secondary processing resources may be accessed without impacting data traffic along the bus. The local bus employs a message control method and apparatus which includes the ability to assert a WAIT signal when the processing resource is replying to a request. By asserting the WAIT signal all other operations on the bus are delayed until the transfer is complete. The use of the WAIT signal enables a device operating at a different speed from the primary processing resource to respond across the bus in a manner that is synchronized to the clock speed of the primary processing resource.

Decentralized bus arbitration using distributed arbiters having circuitry for latching lockout signals gated from higher priority arbiters

Abstract: A silicon semiconductor wafer containing a plurality of silicon integrated circuits formed therein or attached thereto contains at least one data bus to which some of the circuits are connected. Each of the circuits coupled to the data bus contains an arbitration request circuit which selectively passes a signal that requests that its circuit be given access to the data bus so it can transmit information to another circuit on the wafer. In addition, each of the circuits coupled to the data bus has an arbitration circuit which detects which of any of the circuits coupled to the data bus is requesting access to the data bus and facilitates its circuit gaining access to the data bus if its circuit has a higher preselected priority than any other circuit which is simultaneously seeking access to the data bus. The distribution of the arbitration request circuits and of the arbitration circuits simplifies layout and tends to improve the speed of operation.

Transmission-reception equipment for a bus system

Abstract: Transmission-reception equipment for a bus system and for handling access collision of subscriber stations connected dc-free in a bus system preferably constructed with a shielded twisted-pair cable. The transmission-reception equipment of the subscriber stations at their transmission sides, has a difference bus transmitter unlocked for only a fraction of a bit time span and thereby outputting a difference voltage pulse of one the other operational sign but placed in a quiescent condition in the remaining part of every bit time span. At the reception side of the subscriber stations, two difference bus receivers are connected to the bus signal conductors, oppositely in comparison to one another, and a bi-stable RS flip-flop has its inputs connected to outputs of the difference bus receivers.

Multi-computer system of the same architecture with cooperative capability and the cooperating method thereof

Abstract: A homogeneous multi-computer system comprises a system bus with a system data bus for transmitting data and a system management bus for transmitting system management signals, and a plurality of cell-computers having identical architecture and being connected to the system bus. Each cell-computer has a window device (WD), connected between an internal data bus (IDB) of the cell-computer and the system data bus, for controlling the on-and-off states of the system data bus to the IDB; an encoding and selecting device (NCD), connected to the IDB and system management bus, for generating a signal CST and a selected signal NCS representive of match of code sent by the system management bus with code of the present computer; a multi-computer control device (MCD), responding to the selected signal NCS from the NCD and under the trigger of the CST signal from the system management bus, for generating a set of control signals (chfo, SYNC, CPT) and SSYNC signal to each cell-computer via the system management bus for each cell-computer to enter synchronous state; and a central processing unit (CPU), responding to the set of control signals from the MCD, for continuously generating signals during each machine cycle to determine whether the IDB and system data bus are on and the CPU, memory, and I/O devices are high impedance with respect to the IDB.

Duplex data processing system with programmable bus configuration

Abstract: A duplex data processing system includes two processors each provided with a bus connecting unit which disconnects the associated CPU bus from the cross connection bus in a separate mode or connects the CPU bus to the cross connection bus in a duplex mode. The system operates with a logically unified CPU bus through the connection of the internal CPU buses by the two bus connecting units in both processors.

Data processing system with overlap bus cycle operations

Abstract: A data processing system including several devices connected to an asynchronous communications bus for communications between these devices. The communications bus includes a protocol that requires only a single device to regulate communication between devices at any one time. This regulating device is termed the bus master and the remaining devices are termed slaves. This protocol provides the capability for a slave device to indicate to the bus master that a new bus master is to be designated for a temporary communication. This communication with a different bus master then occurs during the communication of the designated bus master.

Interleaved access to global memory by high priority source

Abstract: A digital signal processor includes a global RAM that is accessable by an external high priority bus, a microprocessor and an I/O controller. The global RAM is accessed by a global address bus and a global data bus. The global address bus is coupled by separately selectable buffers to a microprocessor address bus, the external address bus, and an I/O bus, respectively. The global data bus is coupled by separately selectable transceivers to the microprocessor data bus, the external bus, and the I/O bus, respectively. Either the microprocessor or the I/O port controller may request and be granted access to the global memory at any time if it is not already being accessed. If the external bus requests access to the global RAM and either the microprocessor or the I/O port controller is accessing the global RAM, multiple wait states are inserted into that microprocessor or I/O port controller until the external bus completes its access. The microprocessor or I/O controller then automatically continues accessing the global RAM.

Method and device for setting the addresses of subscribers connected to a bus

Abstract: The subject of the invention is a method and device for setting the addresses of subscribers which are connected to a bus, and via the bus to a central processing unit. The subscribers (3, 4, 5) are connected in series in daisy-chain fashion, via a separate control line (9) from the central processing unit (2). By a signal with a defined binary value on the control line (9) at the input to a subscriber (3, 4, 5), the subscriber accepts an address which is assigned to it from a transmission telegram, which is generated in the central processing unit, on the bus, and outputs the defined binary value to the control line. If the signal with the defined binary value at the input of a subscriber (3, 4, 5) fails, the daisy-chain connection is broken. If the daisy-chain connection exists, each subscriber outputs the received address to the bus (1), as the response to the poll of the central processing unit.

Dual bus system

Abstract: The data processing system, has at least one memory unit operatively connected to a memory bus, and further has an input/output (I/O) bus controller for interfacing at least one peripheral device to the data processing system. The data processing system comprises a first bus which provides a first transmission medium between the peripheral device and the memory bus. A second bus, provides a second transmission medium between a CPU and the memory bus. A logic element, interposed between the first and second bus, and the memory bus, interfaces the first and second bus to the memory bus in response to request signals from the first and second bus.

Communication system having interrupts with dynamically adjusted priority levels

Abstract: A communication system includes a processor, memory circuits and a plurality of interfaces for interfacing to data devices. The processor services the interfaces using an interrupt bus including unidirectional inbound and outbound buses. The inbound bus includes one lead for each interface, with each lead having a fixed priority level assigned by the processor. Each interface has access to all leads of the inbound bus. The processor sends commands over the outbound bus to dynamically control the connection of an interface to a lead of the inbound bus.

An input output interface controller connecting a synchronous bus to an asynchronous bus and methods for performing operations on the buses

Abstract: In a data processing system, an input output bus unit (IOBU) is connected to one end of an input output interface controller (IOIC) via an asynchronous bus. The other end of the IOIC is connected to a storage controller (SC) and an input output interface unit (IOIU) via a synchronous bus. The SC and IOIU are connected to a memory unit and an instruction processing unit. The asynchronous bus, which is comprised of three sub-buses and a control bus, conducts signals between the IOIC and an IOBU in an asynchronous "handshaking" manner. The synchronous bus, which is comprised of two sub-buses and a control bus, conducts signals between the IOIC and the SC/IOIU in an synchronous manner. The IOIC, interconnected between the synchronous bus and asynchronous bus, functions as a buffer between the faster synchronous bus and the slower asynchronous bus. Various operations are performed between an IOBU and the memory unit via the asynchronous bus, IOIC, synchronous bus, and SC/IOIU, such as a unit operation, a storage operation, and a message acceptance operation.

Buzz-Net: A Hybrid Token/Random Access LAN

Abstract: Buzz-net is a local network supported by a pair of unidirectional buses to which stations are connected via passive interfaces. The access protocol is a hybrid which combines random access and virtual token features. More precisely, the network operates in random access mode at light load and virtual token mode at heavy load. Because of the virtual token implementation, Buzz-net retains high efficiency even at very high bus speeds. Efficiency at high speeds and bus unidirectionality make Buzz-net particularly suitable for fiber optics media. This paper describes the protocol, develops approximate analytic models for performance evaluation, and compares Buzz-net performance results to those of other unidirectional bus schemes.

Optical bus communication system utilizing frame format signals

Abstract: An optical bus type communication system comprises a bus type transmission line consisting of an optical fiber, a light source provided at the one end of the bus type transmission line for sending an optical signal having a constant level to the bus type transmission line, a plurality of optical switches mounted on the bus type transmission line, and a plurality of terminal interfaces. Each terminal interface sends data by switching the corresponding optical switch so that the optical signals on the transmission line are modulated with the data.

Modular input device system

Abstract: A computer terminal work station having multiple peripheral units simultaneously interconnected into the terminal. A micro processor controller is provided in the terminal and a micro processor slave is provided in each of the peripheral units. Each unit is provided with a bus segment and means to interconnect the bus segments to each other. A single cable extends from the terminal to one of the peripheral units to be connected to the bus segment of that unit, and thereby to the bus segments of all the interconnected units. The units are selectively mechanically interlocked as desired.

Collision avoidance in a multinode data communication network

Abstract: Apparatus and method for collision avoidance in a multinode data communications bus, the bus having a plurality of nodes coupled thereto for transmitting and receiving data over the bus, the bus further including a BUS BUSY signal line bidirectionally connected in common between the nodes, each of the nodes being operable for asserting the BUS BUSY signal line and also for determining the state of the BUS BUSY signal line. In accordance with the invention there is disclosed, for a node having data to transmit on the bus: (a) testing the state of the BUS BUSY line to determine if the line is asserted; (b) asserting, if the line is determined not to be asserted, the BUS BUSY line for a first predetermined interval of time; (c) deasserting the BUS BUSY line for a second predetermined interval of time; (d) testing the state of the BUS BUSY line to determine if the line is asserted; (e) asserting, if the BUS BUSY line is determined to be not asserted, the BUS BUSY line; (f) transmitting the data; and (g) deasserting the BUS BUSY line.

Method and apparatus for error recovery in a multibus computer system

Abstract: A bus adapter interconnecting a system bus and an I/O bus over an interconnect bus generates a first READ signal by decoding the command lines of the I/O bus and supplying the READ command signal across the interconnect bus. The command lines are also provided across the interconnect bus and are decoded on the system bus side of the interconnect bus to form a second READ signal. The first and second READ signals and a parity error signal are processed on the system bus side of the interconnect bus to generate a NON-RECOVERABLE ERROR signal to initiate a system shut-down when a parity error occurs during a disconnected WRITE transaction and to generate a RECOVERABLE ERROR signal to initiate a repeat of the transaction when a parity error occurs during a READ transaction.

Node adapted for backplane bus with default control

Abstract: A node for communicating with a plurality of other nodes in a computer, the node including logic circuitry for transmitting and receiving data at first and second logic levels. A default generator is connected to an arbiter and responds to a lack of request activity and the absence of a multi-cycle data transfer being performed on the bus and causes the bus to be driven to one of the first and second logic levels.

Serial data bus for different modes of operation (SCI, SPI and buffered SPI) and methods for a serial peripheral interface in a serial data bus

Abstract: The aim of the Chrysler Collision Detector (CCD) Bus System is to allow multiple microprocessors to easily communicate with each other over a common pair of wires (called a bus) using a scheme similar to a telephone party line. All microprocessors connected to the bus are able to receive all messages transmitted on the bus. Any microprocessor with a message to transmit on the bus waits until any current user is finished before attempting to use it. Whenever the bus is available, its use is allocated on a first-come, first-serve basis (i.e., whichever microprocessor first begins transmitting its message on the bus after any previous message finishes gets the use of the bus). If, however, multiple microprocessors attempt to begin transmitting their messages on the bus at exactly the same time, then the message with the highest priority wins the use of the bus. All messages have unique message priority values and each message is transmitted by only one microprocessor. The subject invention provides the ability to communicate with a SCI port, a SPI port or a buffered SPI port. This allows communication with any device configured with any one of these ports, all on the same bus. In a communication system for the transmission of messages through a data bus between one or more user microprocessors coupled to the data bus, the user microprocessors having either a serial communications interface (SCI) port or a serial peripheral interface (SPI) port along with a clock port and an input / output port, the user microprocessors being coupled ton the data bus by a bus interface integrated circuit, a method to transmit and receive data in an SPI mode of operation in conjunction with a method of arbitrating data on the data bus, and a method to transmit and receive data in a buffered serial peripheral interface (SPI) mode of operation in conjunction with a method of arbitrating data on the data bus.