Showing papers on "Bus network published in 1988"

Detection and identification of topology errors in electric power systems

Abstract: A method for detecting topology errors in electric power networks is developed by providing a geometric interpretation of the measurement residuals caused by such errors. A test for single topology errors is presented that is similar to the normalized residuals test for measurement errors. This test is generalized to multiple topology errors. The concept of critical network branches (where their removal renders the network unobservable) is introduced and extended to critical-branch k-tuples. It is shown that topology errors on critical branches cannot be detected from measurement residuals. An equation is developed for a matrix whose column linear dependencies determine topology error detectability and identifiability. An example for an IEEE 14 bus network is provided. >

Optimization of feeder bus routes and bus-stop spacing

Abstract: Existing studies of transit network design deal separately with the problems of determining the optimal route spacing and operating headway, and that of determining the optimal stop spacing. This paper presents an analytic model for the design of an optimal feeder bus network for accessing an existing rail line, which avoids the sequential approach and combines these three basic variables. Our results with regard to bus‐route spacing and headway are similar to those obtained previously, indicating that route spacing and operating headway are not highly sensitive to changes in the relevant system parameters. With regard to bus‐stop spacing, three different cases are considered, reflecting three different stop‐spacing policies. In the first case, bus‐stop spacing is specified as uniform over the entire area. In the second case, stop spacing is constant along any given route. In the third case, stop spacing may vary both between and along routes. Closed‐form solutions are presented for the first two cases. T...

On-board network for motor vehicles

Abstract: The on-board network for motor vehicles contains a multiplex control for switching, controlling and monitoring electrical end devices such as switches, operating and indicating elements, sensors and actuators and consists of several bus interfaces (2) coupled to a common bus line (1). The network also includes control devices (4) associated in star configuration via signal lines with the bus interfaces and end devices associated with the control devices. The control devices (4) contain signal converters and a data processor as well as transmitters/receivers for exchanging data signals with the corresponding bus interface. The operation of the on-board network is accomplished in such a manner that the transmission of the data signals from one bus interface to the associated control devices is controlled by the bus interface and follows cyclically the respective control device in the sequence of the groups of inputs and outputs. The control devices can deliver here, for transmitting a critical signal value to the corresponding bus interface device at predetermined points of the transmission cycle, a signal which leads to the interruption of the transmission cycle.

Bus arbitration controller

Abstract: A bus arbitration controller controls access of a plurality of asynchronous potential master devices to a unitary interconnecting bus by forming a distributed state machine of arbitration logic units in each of the potential master devices Each arbitration logic unit receives control signals by way of the unitary bus which are common to all the devices, each control signal being the logical OR of the corresponding signals from all other devices The control signals include a device address/priority number and a synchronization signal set The arbitration logic includes a priority resolver which awards bus access to a device having the highest address/priority number, and control logic which receives the common synchronization signal set and synchronizes the operation of the device in which the arbitration logic resides with all other devices contending for the unitary bus The control logic and the priority resolver are programmable array logic circuits

Function-distributed control apparatus

Abstract: A function-distributed control apparatus comprises a first bus, a second bus, and at least one base processor element which includes a first main processing unit connected to at least the first bus, a second main processing unit connected to at least the second bus, and a dual-port memory with a mutual interrupt circuit connected to both these main processing units for communications between them. The first bus and the first main processing unit are chiefly for intelligent processing required for controlling a machine, while the second bus and the second main processing unit are chiefly for motion control of the machine. Those buses are also connected to various intelligent subsystems each including a processing unit and a dual-port memory with a mutual interrupt circuit for communications with the base processor element.

Input/output system for multiprocessors

Abstract: In a digital computer system which employs a plurality of host processors (33), at least two system buses (35) and a plurality of peripheral input/output ports, an input/out­put system is provided whereby ownership of the input/output channels (109) is shared. The device controller (41) employs a first port controller (43-0) having a first ownership latch, a second port controller (43-1) having a second ownership latch, a first bus, a dedicated microprocessor having control over the first bus (the MPU bus), a second, higher-speed bus, a multiple-channel direct memory access (DMA) controlIer which is a state machine which controls the second bus (the data buffer bus), a bus switch for exchanging data between buses, a multiple device peripheral device interface, namely a Small Computer System Interface (SCSI) (111), and at least provi­sion for interface with data communication equipment (DCEs) or data terminal equipment (DTEs). The DMA controller arbitrates data bus usage and can allocate alternate bus clock cycles in response to requests to exchange data and is capable of supporting overlapping transfers. The microprocessor is allowed access to the data buffer bus only if the data buffer bus is not in use for data transfer. The latches associated with each port grant ownership to either port or both ports allowing data exchange between addressed peripheral devices and requesting ports.

Hierarchical multiple bus computer architecture

Abstract: A modular and hierarchical multiple bus computer architecture in which the master bus and slave bus are substantially identical, and communicate through a combination of an interface controller and a shared dual port RAM responsive to a shared RAM controller. Processor engine modules including a bus, a processor, an interface controller, a shared dual port RAM, and a shared RAM controller are horizontally and/or vertically integrated at multiple levels without major restructuring of the composite system control operations by having each slave processor engine module interface as a peripheral upon the bus of its master. The modularity of the architecture allows the use of standard peripherals and platform processor engines to expand memory or increase functionality without burdening the master bus processor engine. Each slave bus processor engine is fully functional as an independent processor with mastery over its own bus. The architecture is particularly efficient in extended data base, fault tolerant data base or multi-communication system adapter interface functions.

Diagnostic error injection for a synchronous bus system

Abstract: Bus error injection circuit generates bus errors to test proper operation of bus error detection and recovery in a system of modules interconnected by a synchronous digital bus. Application of the circuit is bus error detection and recovery tests for a physical realization of the system. The bus error injection circuit can be replicated on a number of modules interconnected by a synchronous bus to provide multiple sources of error injection. One module, or multiple modules, with error injection circuitry is designated as the source(s) to inject a transient bus error. The bus error injection circuitry monitors the bus to determine when the module is a participant in a bus transfer cycle on the bus. An error injection counter decrements for each such cycle. When the counter output value is one, the module derives its error injection pattern onto bus signal lines in place of the signal line values normally generated. When the counter output reaches zero, the count enable is disabled and the signals normally supplied for the next bus cycle are enabled to the bus.

Method and apparatus for self-timed digital data transfer and bus arbitration

Abstract: A self-timed bus arbitration and digital data transfer system is provided for a computer network having multiple master and slave devices sharing a digital data bus. Each master device includes a bus arbitration logic circuit having a time delay element. Each master contending for access to the data bus outputs an identifier on signal lines connecting the master devices. After a period of time comprising the slowest master's operational delay, the bus arbitration circuits determine, on a prioritized basis, which particular master shall have access to the data bus at that time. Upon gaining access, the particular master provides a request signal on a control line connecting the master and slave devices and provides an address on an address bus that may be multiplexed with the data bus. After each slave has decoded the address, as determined by the slowest slave's delay, an acknowledge signal is provided on the control line to the particular master so that data transfer may proceed to/from the selected slave. When the data transfer is complete, the selected slave signals the particular master to release the data bus for subsequent operations. Bus arbitration for a subsequent operation may be performed during the current data transfer. All operations are self timed in that they do not require a bus clock, but they are constrained through wired-OR logic circuitry by the slowest device connected to the system, which includes all delays resulting from bus length, buffers, and environmental conditions.

Multiple port bus interface controller with slave bus

Abstract: A new integrated circuit for interfacing a standard IEEE 796 bus to a VSB-type buffer bus. This integrated circuit includes a DMA channel for high speed access of the IEEE 796 bus to the buffer bus, and a slave bus channel for high speed access of the buffer bus to the IEEE 796 bus. A third bus interface connects to a local processor to assist in arbitration and control during some types of data transfers.

Push-pull serial bus coupled to a plurality of devices each having collision detection circuit and arbitration circuit

Abstract: A high speed serial bus is disclosed have particular application for use in passing messages in a multiple processor computer system. The serial bus includes a three-wire serial link having lines identified as "SDA", "SDB" and "ground". The ground line provides a common reference for all devices coupled to the serial bus. A message controller is coupled to each agent for transmitting and receiving serial data along the bus. Both lines of the serial bus as well as the ground are coupled to a bus state detector in the message controller which provides three basic signal outputs. The bus state detector determines whether or not the bus is in use, a collision has occurred between messages, and decodes data received on the bus. Data which is transmitted along the serial bus is driven on lines SDA and SDB 180 degrees out of phase relative to each other. The message controller encodes messages to be transmitted using, in the present embodiment, well known Manchester encoding techniques. A bus idle state occurs when all transmitters are off allowing both lines SDA and SDB be pulled high by pull-up resistors. Valid data states may occur any time a single transmitter is transmitting. When two or more transmitters begin transmitting a collision state exists. The message controller recognizes collisions and provides a back-off algorithm.

Star topology local area network

Abstract: A star topology local area network comprises a data bus, a receive-not-ready bus, a plurality of bus access units associated respectively with user terminals for receiving a request therefrom, and an arbiter for assigning priority to one of the bus access units when requests for transmission occur simultaneously. Each of the bus access units comprises a transmit buffer for storing a packet from the associated user terminal and forwarding it to the data bus when priority is assigned to it and a receive buffer for storing a packet from the data bus and forwarding it to the associated user terminal. An address filter is provided in each bus access unit to detect a packet addressed to it and applies a receive-not-ready signal to the receive-not-ready bus when the receive buffer has an insufficient capacity to receive the detected packet. A bus access controller is connected to the receive-not-ready bus for terminating the transmission of a packet in response to the receive-not-ready signal. The storage capacity of the transmit buffer is also monitored and a proceed-to-send signal is transmitted from the bus access unit to the associated user terminal indicating the permission of transmission when the detected storage capacity is sufficient to receive a packet from the terminal.

Network system using token-passing bus with multiple priority levels

Abstract: A network system using a token-passing bus access method, comprising bus type transmission path, nodes for executing a priority processing algorithm based on a standard of an IEEE 802.4 token-passing bus, common memories respectively included in the plurality of nodes and each having a mutually common address structure, and communication circuits, respectively included in said plurality of nodes, for communicating storage contents among the common memories through the transmission path in accordance with priority levels of the priority processing algorithm.

Performance analysis of multiple bus interconnection networks with hierarchical requesting model

Abstract: The authors study the performance of multiprocessor systems employing multiple buses as the interconnection networks under a nonuniform requesting model, called the hierarchical requesting model. The effective memory bandwidth is chosen as the performance measure. The networks investigated include multiple bus networks with full bus-memory connection, multiple bus networks with single bus-memory connection, and multiple bus networks with partial bus-memory connection. The authors also propose a type of multiple bus network with partial bus-memory connection, called partial bus networks with K classes. The N costs and fault-tolerant capabilities of the multiple bus networks are also evaluated and compared to one another. It is shown that the partial bus networks with K classes are useful in applications requiring high performance and degree of fault tolerance with moderate cost. >

Interprocessor bus switching system for simultaneous communication in plural bus parallel processing system

Abstract: A bus switching apparatus and method for multiple processor computer systems comprises a plurality of bus switches interconnected by branch buses. Each processor or other module of the system is connected to a spigot of a bus switch. Each bus switch also serves as part of a backplane of a modular crate hardware package. A processor initiates communication with another processor by identifying that other processor. The bus switch to which the initiating processor is connected identifies and secures, if possible, a path to that other processor, either directly or via one or more other bus switches which operate similarly. If a particular desired path through a given bus switch is not available to be used, an alternate path is considered, identified and secured.

External expansion bus interface

Abstract: A computer bus interface suited to connecting an expansion bus to a computer's internal bus The interface is capable of selecting and deselecting any devices coupled to the expansion bus by enabling and disabling buffers which intercept signals between the expansion bus and the internal bus

Method and apparatus for interconnecting busses in a multibus computer system

Abstract: A bus adapter connecting a high-speed pended bus (25) to a slower speed non-pended bus (45) includes a first module (69) functioning as a node of the pended bus and a second module (61) functioning as a node of the non-pended bus. An interconnect bus (611) extends between the two modules. Control signals on the interconnect bus generated by the first module comprise status signals having an indefinite assertion duration, and are deasserted only in response to control signals on the interconnect bus generated by the second module, which have a finite duration. Control signals on the interconnect bus generated by the first module are synchronized by a dual-rank synchronizer controlled by two phases of a multiphase clock signal derived from the clock signal of the non-pended bus. Control signals on the interconnect bus generated by the second module are synchronized by a dual-rank synchronizer controlled by two phases of a multiphase clock signal derived from the pended bus clock signal.

Remote storage management mechanism and method

Abstract: The flow of work requests in a server driven process to process communication environment is described. Logical connections between processes and bus managers interfacing bus units to an I/O bus are assigned to connection groups for management by the bus managers. Each bus unit has its own connection groups for the logical connections. Bus unit resources are assigned to each connection group based on performance factors, and a series of bus unit messages are used to control the flow of work so that a group which has no more resources will not accept further work requests. The originator of the work requests will resequence rejected work requests and resend them when the connection group has freed up resources. A further mechanism is provided to facilitate work consistent with the server driven architecture when bus units do not have adequate DMA capabilities. Two ways of reversing control of transfer of work requests and data so that the server need not have master DMA capability are presented. Management of storage in a remote processor is used to transfer work and its associated data into storage accessible by a bus unit with slave DMA capability. The slave DMA bus unit then transfers the information into storage is manages. In another way of reversing the flow, a bus unit message is used to make the original server a requestor. The bus unit message contains information which varies the request sent by the requestor. In this manner, the server, which was the original requestor transfers information using its master DMA capability flow.

Apparatus and method for extending a parallel synchronous data and message bus

Abstract: An input/output bus for a data processing system which has extended addressing capabilities and a variable length handshake which accommodates the difference delays associated with various sets of logic and a two part address field which allows a bus unit and channel to be identified. The various units can disconnect from the bus during internal processing to free the bus for other activity. The unit removes the busy signal prior to dropping the data lines to allow a bus arbitration sequence to occur without slowing down the bus.

System for testing internal nodes

Abstract: The testing circuit for testing internal nodes of a device includes storage for storing the test addresses of selected internal nodes in the device. A decoder responds to a test command from a microprocessor for selecting the test addresses from the storage and supplies the test addresses to an address bus in place of other addresses supplied to the address bus. A test decoder responds only to the test addresses on the address bus for enabling the transfer of data between the selected internal nodes in the data bus for testing the selected internal nodes.

Signal processing system including a bus control module

Abstract: A signal processing system that includes a ring bus; a multiplicity of system modules, each coupled to the ring bus and operative to receive and transfer blocks of data words over the ring bus; and a bus control module coupled to the ring bus and operative to support simultaneous data transfers between specified pairs of system modules in accordance with concurrent execution of multiple programs of data transfer instructions. In an alternate embodiment, the signal processing system may include a plurality of ring buses wherein each system module is coupled to all of the ring buses and operative to receive and transfer blocks of data words over any one of the ring buses. In addition, the bus control module is also coupled to all of the ring buses and operative to support simultaneous data transfers between specified pairs of system modules over all of the ring buses. Moreover, each ring bus may comprise individual bus segments for system module to system module coupling about the ring.

Extended bus controller

Abstract: An extended bus controller includes a base module including at least a first peripheral control unit connected to a base bus, a central processing and controlling unit, and a memory unit; an extension module including at least a second peripheral control unit connected to an extended bus; a connection bus interconnecting the base bus of the base module and the extended bus of the extension module; a direct memory access control unit provided for at least one of the base module and the extension module for directly controlling data transfer between the first and second peripheral control units and the memory unit; a first master clock generator unit for supplying first master clocks to the direct memory access control unit and controlling the direct memory access control unit, the first master clocks having a first frequency determined by a data transmission delay time of at least one of the base bus, the connection bus and the extension bus, and by the performance of the first peripheral control unit and the memory unit; and a second master clock generator unit for supplying second master clocks to the direct memory access control unit and controlling the direct memory access control unit, the second master clocks having a second frequency determined by a data transmission delay time of at least one of the base bus, the connection bus and the extension bus, and by the performance of the second peripheral control unit and the memory unit.

Method and apparatus for identifying defective bus devices

Abstract: A technique for automatically diagnosing the failure of electronic devices connected to share a common bus. All bus devices are first disabled, and the bus is examined to determine if a failed device is interfering with normal operation by causing the bus to be stuck at a logic high or a logic low level. If the bus is stuck low or high, a forcing voltage nearly equal to either V ol or V oh , respectively, is applied to the bus, with all devices still disabled. A disabled bus current is then measured. One at a time, the bus devices are enabled, and the current on the bus measured to determine an enabled bus current. If, for a particular device, the enabled bus current exceeds the disabled bus current by a predetermined amount depending on the drive current specification of the device, it is concluded that the particular device is operating properly.

Method and apparatus for testing three state drivers

Abstract: In an integrated circuit chip utilizing CMOS technology, an embedded data bus is driven by embedded three state drivers, and the bus is in turn connected to provide a drive signal to embedded receivers and similar logic devices. An embedded threshold detector is provided to detect the occurrence of any invalid data signal (i.e. a non-"0" or a non-"1" signal level) on the data bus. The threshold detector's output signal is connected to off chip terminal means, to thereby enable off chip monitoring of the bus signal. The threshold detector's output signal is also ANDed with the bus signal, to thereby prevent the application of a potentially destructive invalid bus signal to the receivers and the like. Terminator circuit means provides a known invalid signal state on the bus when the bus is in its high impedance state due to all of the three state drivers being disabled.

Advance polling bus arbiter for use in multiple bus system

Abstract: An advance polling bus arbiter includes a priority selector for selecting during a polling cycle a highest priority source system unit which is seeking access to a system bus. Bus grant logic sends the highest priority source system a bus grant signal which indicates that the selected system unit can make a transfer during the next cycle. An advance link logic unit compares a target bus address received from the selected system unit to a local bus address and simultaneously signals an intersystem bus link of an impending intersystem transfer while the source system unit is receiving its bus grant signal.

Setting target rotation times in an IEEE token bus network

Abstract: The IEEE standard 802.4 token bus protocol requires each network station to implement a synchronous (highest priority) message class, and permits a station to implement three lower priority classes: urgent asynchronous, normal asynchronous, and time available. Each of the lower three priorities (called access classes) is assigned a target token rotation time that limits the amount of time that a station can use to service lower priority traffic. A formulation of the problem is presented in which messages are transmitted from an access class as long as network throughput remains below a user-specified threshold. Formulas are derived that transform this priority scheme, based on network throughput limits, into the proper target rotation time settings that the token bus protocol actually requires. The analytical model is compared with a computer simulation of the token bus protocol and shows close agreement. >

Input/output bus expansion interface

Abstract: An I/O bus expansion interface is disclosed which enables an I/O device having an n-bit data bus to be interfaced to an m times n-bit I/O data bus of a host processor. This I/O bus expansion circuit maximizes the computer processor's performance by providing full I/O data bus bandwidth and allowing overlap of processor execution and I/O bus expansion interface circuit operation. This is accomplished by: (1) prefetching multiple control and/or data fields from the I/O device and presenting that information to the host without delay and (2) burst writing multiple fields from the host to the bus expansion interface circuit, without delay of the host, and thereafter making these fields individually available to the I/O device.

Bus structure for overlapped data transfer

Abstract: An improved system bus structure for versatile use in various digital computer architecture configurations, particularly those of mini-supercomputers, and, designed to support high speed, high reliability, parallel processing of bi-directional signal transfers in a multi-port and multiple central processor unit (CPU) communication environment as between system bus units or devices. The system bus structure may be sized for a compact encasement and may carry as many as 129 simultaneous signals to and from various units connected to it. The system bus structure includes enabling structure for a centralized arbitration system, a centralized clock and synchronized transfer system, a centralized transfer monitor, a centralized parity error assessor and signalling system including transfer termination, and, a memory/inter-system inhibit system.

Multipurpose bus interface

Abstract: A multipurpose bus interface circuit for interfacing a first communications bus to a second communications bus where at least one of the buses is a command/response time division multiplexing data bus. The interface circuit includes a main controller for controlling the transfer of data between the first bus and a RAM. A microstore contains the software for the main controller, the software controlling the handling and interpretation of data to and from the first bus and processed by the main controller. A co-processor has direct access to the RAM and performs primarily the data processing function of the interface circuit. An interface module provides interface between the RAM and the second bus, the module formatting the data transmitted between the RAM and the second bus, whereby the main controller performs primarily to handle the input/output functions and the co-processor performs primarily to handle the data processing functions of the interface circuit.

Synchronized processing system with bus arbiter which samples and stores bus request signals and synchronizes bus grant signals according to clock signals

Abstract: A digital system bus arbiter network which provides prioritized but equal opportunity for various devices to gain access to a common bus. The network samples the state of all pending requests for bus access, stores the current requests and generates a sequence of bus access granting signals in an order determined by the priority of the stored bus requests. When all of the bus requests have been processed for a given sample period, the network resamples currently pending bus requests and repeats the process of generating the sequence of bus granting signals on a prioritized basis. The network guarantees an equal share of bus bandwidth to each device.