Showing papers on "Bus network published in 1989"

High-capacity lightwave local are networks

Abstract: The author presents an overview of fundamental considerations that guide and motivate research in this area. He explores the relationship between the bandwidth of the fiber, the available power and the loss in various network designs, and the throughput of networks as limited by the medium-access techniques and control mechanisms. He discusses two approaches to opening up the bottleneck that seem particularly promising. The first, multihop, uses a novel network architecture to achieve high capacity with existing devices; the second, wavelength division multiple access (WDMA), emphasizes new devices in a relatively conventional architecture. Noting that the primary disadvantage of the bus topology, poor energy efficiency, could be overcome with a suitable optical amplifier to compensate for the high signal attenuation in the network, the author discusses one of the most promising candidates, the traveling-wave semiconductor amplifier. He also discusses medium-access considerations. >

Communication processor for a packet-switched network

Abstract: A packet switch receives data and processes it for assembly into packages. A bus allows communication between each of the data processing units of the switch and one or more storage units for storing the data packets. Arbitration for deciding which of the processing units will be granted access to the bus is performed by a system which selectively and alterably designates any of at least two different levels of priority of access to the bus for each of the processing units, and the relative percentages of time of access for the different priorty levels. The system assures greater access to the bus by those of the processing units having the higher level of priority. If communication is provided by two buses, the requests for access are alternated between them. The arbitration system provides selective access to the bus in any of a plurality of bus cycles including a read cycle, a write cycle and a read/modify/write cycle, and grants a request for access from a higher priority processing unit within one bus cycle.

High speed bus with virtual memory data transfer and rerun cycle capability

Abstract: A high speed data transfer bus with virtual memory capability. The bus has particular applications in computer systems which employ peripheral devices. The bus allows high speed data transfer through the use of a virtual memory scheme. This minimizes the number of lines required to implement the bus and minimizes the amount of time a particular device is required to wait before it can access the bus and complete a data transfer. Control signals are employed that are driven both active and inactive, facilitating interfacing the bus to low-power CMOS technology.

The feeder-bus network-design problem

Abstract: The potential for improving the cost-effectiveness of public transport operations by designing better integrated feeder-bus/rail rapid transit systems has been widely recognized. This paper defines the feeder-bus network-design problem (FBNDP) as that of designing a feeder-bus network to access an existing rail system. The FBNDP is considered under two different demand patterns, many-to-one (M-to-1) and many-to-many (M-to-M). We present a mathematical programming model for the M-to-1 FBNDP, and show that it can be generalized to the M-to-M FBNDP. The FBNDP is a large and difficult vehicle-routeing-type problem with an additional decision variable—operating frequency. A heuristic model is presented, which generalizes the ‘savings approach’ to incorporate operating frequency. The computational analysis shows that the proposed heuristic provides reasonable feeder-bus networks and consistent responses to ‘what if’ questions. A comparison indicates that the proposed heuristic provides solutions that are superior to manually designed networks. The advantages of this heuristic are particularly significant under variable demand.

Supercube: An optimally fault tolerant network architecture

Abstract: A new class of interconnection network topology is proposed for parallel and distributed processing. The attractive features of this class include (a) the network can be constructed for any number of computing nodes, (b) the network is incrementally expandable, i.e., a new node can easily be added to the existing network, (c) it has good fault-tolerant characteristics (measured by the connectivity of the network graph) and (d) it has small delay characteristics (measured by the diameter of the network graph). The node connectivity of the network is equal to the minimum node degree. In this sense the network is optimally fault-tolerant.

System scan path architecture with remote bus controller

Abstract: A system scan path architecture is provided by a device select module (DSM) (18) which may be used in conjunction with associated circuits (16a-b) to select secondary scan paths (PATHl-m) on each circuit for coupling with a primary scan path on a test bus (14). The test bus (14) is controlled by a primary bus master (12). Remote bus masters (124) may be used in conjunction with the DSMs (18) to provide serial-scan testing independent of the primary bus master (12).

Parallel microprocessor architecture

Abstract: A multicomputer chip has a common bus and up to ten microcomputers connected in parallel to the common bus via routers contained in the microcomputers. The common bus can be connected to an external bus by means of a router mounted on or off the chip. Any defective computer found during testing can be rendered inactive by assigning it an unused address and, in this way, the remaining computers are unaffected. Instead of providing each multicomputer on a separate chip, a complete wafer may be manufactured so that it contains many of the multicomputers. A hierarchical bus system interconnects the multicomputers so as to permit efficient routing of data between the various computers.

Extended multistation bus system and method

Abstract: A multistation computer system includes a host computer and a plurality of workstations coupled to the host computer by a communications bus. The host computer is coupled to the communications bus by a host controller and each workstation is coupled to the communications bus by a workstation controller. When the host computer performs a data transaction with a workstation, the host controller monitors the bus signals on the host computer and determines which workstation is being addressed. The host's bus signals are then encoded and sent to the appropriate workstation in a data packet transmitted over the communications bus. In the preferred embodiment the encoded bus signals are transmitted over an optical fiber bus which is daisy chained to all the workstation in the computer system and then back to the host computer. At the workstation the encoded bus signals are decoded and then asserted on the workstation's bus. Signals sent by the workstation back to the host computer go through a similar encoding, transmission and decoding process. The system thereby mimics the operation of a workstation which is directly coupled to the internal bus of the host computer. Memory or data transfers from the host to any workstation are immediately acknowledged by the apparatus of the present invention, even though the data has not yet been received by the workstation. This allows the host to immediately move on to its next task without having to wait for the workstation to process the previous data transfer.

Method for transferring information between main store and input output bus units via a sequence of asynchronous bus and two synchronous buses

Abstract: In a data processing system, an input output bus unit (IOBU) is connected one end of an input output interface controller (IOIC) via an asynchronous bus. The other end of the IOIC is connected to a storage controller (SC) and an input output interface unit (IOIU) via a synchronous bus. The SC and IOIU are connected to a memory unit and an instruction processing unit. The asynchronous bus, which is comprised of three sub-buses and a control bus, conducts signals between the IOIC and an IOBU in an asynchronous handshaking manner. The synchronous bus, which is comprised of two sub-buses and a control bus, conducts signals between the IOIC and the SC/IOIU in an synchronous manner. The IOIC, interconnected between the synchronous bus and asynchronous bus, functions as a buffer between the faster synchronous bus and the slower asynchronous bus. Various operations are performed between an IOBU and the memory unit via the asynchronous bus, IOIC, synchronous bus, message acceptance operation.

Multiprocessor system having distributed shared resources and deadlock prevention

Abstract: In a data processing multiprocessor system having distributed shared resources where each system processor (7) is provided with at least a local memory (8) to which it get access through a local bus (11), and with an interface unit (10) for connection of the local bus (11) to a system bus (5) and wherein each of the system processors may have access the local memory of another processor through its own local bus, its own interface unit, the system bus and the local bus of the other processor, deadlock is prevented by providing a bypass unit (40) of the interface unit (10) for enabling access from the system bus to the local bus through the bypass unit, a block (9) connected between the local bus and the interface unit (10) for latching system bus access requests received from an agent processor on the local bus, and a block (12) for isolation of the agent processor outputs from local bus, so that each agent processor may post read/write operations in the related latching block (9) for latching bus access requests and thereafter release its own local bus without awaiting completion of the operation, whereby the local bus is available to receive access requests received from the system bus through the bypass unit (40), the operation pending in the latching block (9) being completed, if a read operation, by reconnection of the agent processor (7) and the latching block (9) to the local bus.

Cpu-bus controller for accomplishing transfer operations between a controller and devices coupled to an input/output bus

Abstract: A synchronous bus controller which provides a functional control link between one or more microprocessors and an asychronous main input/output bus is provided. The bus controller includes a state machine and data bus width determining logic enabling the bus controller to initiate and control access operations between microprocessors and accessible devices on the main input/output bus when the microprocessor and the accessed device may have different data bus widths. The bus controller includes logic circuitry to determine the number of access cycles required to complete a requested access operation and detects the last access cycle of a current access operation to terminate an access operation and provide a ready signal to the microprocessor indicating that the bus controller is ready for the next access request.

Bus arbitration system for concurrent use of a system bus by more than one device

Abstract: A bus arbitration system is disposed between a plurality of devices for granting use of a bus having a data bus size larger than a port size of each of the plurality of devices A plurality of partial buses are made from the full size bus Each of the partial buses has a data bus size equal to the corresponding port size of the devices, and each of the devices is connected to one of the partial buses through a corresponding port unit An arbitration between the plurality of devices for granting use of the bus is carried out for each partial bus through the corresponding port unit

Synchronous bus lock mechanism permitting bus arbiter to change bus master during a plurality of successive locked operand transfer sequences after completion of current sequence

Abstract: A data processing system having a mechanism for changing communication bus mastership when a series of locked operand transfer sequences are executed. The system has at least two processors coupled via the communication bus and a bus arbiter. In one form, a locked transfer end signal is provided by each processor to the bus arbiter so that if a high priority need is recognized by the bus arbiter during early execution of a plurality of locked operand transfer sequences the high priority need can be responded to by the bus arbiter before completion of all of the locked sequences. In another form, control signals are provided by the bus arbiter to each processor to accomplish the equivalent function.

High speed module interconnection bus

Abstract: A method and apparatus for providing communication among N modules connected to a common communication bus uses a bus structure with a reserve line for signaling the occurrence of a reservation time slot during which time each of the N modules which have information to transmit may reserve a time for transmission over the bus. A plurality of at least N data lines are used for transmission of data words over the bus. Each of the N modules are also assigned use of one of the plurality of data lines for signaling during the reservation time slot that the module has information to transmit over the bus. The reserve line is also used for signaling, that a word of data being transmitted over the plurality of data lines is a last word in a current transmission to be transmitted by the module currently transmitting.

Arrangement for transmitting data and supply voltage via a bus

Abstract: The devices (ST1, ST2 ... STn) of a bus system are in each case connected to the bus line (BL1, BL2) by means of a transformer (U1, U2 ... Un) which exhibits two windings (Wi1, Wi2) of the same number of turns which are connected with one of their connections to the bus line and with the other one of their connections to the series circuit of two capacitors (Ci1, Ci2) having identical capacitance. Data signals are coupled in and out via a third winding (Wi3). The supply voltages for the devices (ST1, ST2 ... STn) are supplied via the bus line (BL1, BL2) to the devices (ST1, ST2 ... STn) where they are picked up at the respected series circuit of the capacitors (Ci1, Ci2). The invention is used in the process equipment bus (field bus).

High speed bus with virtual memory data transfer capability using virtual address/data lines

Abstract: An improved high speed data transfer bus with virtual memory capability is disclosed. The bus has particular applications in computer systems which employ peripheral devices. The bus allows high speed data transfer through the use of a virtual memory scheme. Moreover, the present invention minimizes the number of lines required to implement the bus. The present invention also minimizes the amount of time a particular device is required to wait before it can access the bus and complete a data transfer. Moreover, the present invention employs control signals that are driven both active and inactive, facilitating interfacing the bus to low-power CMOS technology.

Insertion and removal of a circuit device into a bus network

Abstract: A circuit device (e.g. mounted on a printed circuit board) is connected to a data network, to which network are also connected a plurality of other circuit devices under power. On removal of such a circuit device, the output driver connecting the circuit components of the output device to the communications bus of the bus network is first disconnected from power, and only when its disconnection is stable is the device withdrawn. A control device of the circuit device is connected to the control bus of the data network, and before power is disconnected from the output driver, the control device signals to the network so as to prevent other circuit devices connected to the network from signalling on the network. Effectively, the circuit device to be removed "occupies" the bus. This occupation is maintained until the disconnection of the output driver is stable, and then the circuit device can be removed from the network. Similarly, on insertion, the network is first occupied before power is connected to the output driver. In this way, it becomes possible to prevent faults due to missignalling between the other circuit devices connected to the network when one circuit device is inserted or removed.

IC card with switchable bus structure

Abstract: An IC card with a bus structure switchable between a narrow bus mode (such as an 8 bit bus) and a wide bus mode (such as a 16 bit bus). A plurality of memories are provided (in the example preferably 8 bit memories). Addresses are coupled to the IC card for activating the memories in parallel when in the wide bus mode or in selectable sequence when in the narrow bus mode. The data lines of the memories are connected by bus switching means to couple the memory data lines to the output bus so that data exchange is in parallel between both of the memories and the 16-bit bus in the wide bus mode, and is between individual ones of the memories and only the 8-bit bus in the narrow bus mode. The result is efficient use of both semiconductor memories in both the wide bus and narrow bus modes, with automatic switching between modes on the IC card in dependence upon a logic signal derived from the external terminal which defines the mode in which the IC card is intended to operate.

Method and apparatus for the dynamic adjustment of data transfer timing to equalize the bandwidths of two buses in a computer system having different bandwidths

Abstract: The bandwidth of a first bus and a second bus, unequal due to differences in protocol overheads and cycle times between the buses, are equalized without sacrificing any bandwidth on the lower bandwidth bus and without introducing any buffering in a control logic device. The control logic device equalizes the bandwidths of the buses by instructing a device coupled to the second bus to insert a partial dead bus cycle in a read transmission thereby dynamically adjusting read timing on the second bus when the second bus is heavily loaded.

Apparatus and method for improving the communication efficiency between a host processor and peripheral devices connected by an scsi bus

Abstract: Apparatus and method for increasing efficiency of command execution from a host processor over an SCSI bus. Arbitration, selection and message out functions of SCSI protocol are implemented using a background arbitration state machine. Additional protocol functions are implemented in a foreground state machine. When the host processor issues a command for access to the SCSI bus, the background state machine can be programmed before the foreground machine completes the protocol function for a previous command. Thus, the background state machine is ready to arbitrate for access to the bus at the very next bus free condition.

Bus device which performs protocol confidential transactions

Abstract: A bus device of a first type uses a first arbitration protocol. The first-type device is designed for use in a computer system having a communications bus, and one or more other bus devices connected to the bus, including possible first-type bus devices which also use the first arbitration protocol and one or more second-type bus devices which use a second, different, arbitration protocol. The first-type bus device includes a protocol specific memory for storing information; means for monitoring the bus to determine whether the current bus master of the bus arbitrated in the manner of the first or second arbitration protocols; and means for denying the current bus master the ability to access information stored in the protocol specific memory if the means for monitoring determines the bus master arbitrated according to the second arbitration protocol.

Memory error correction system distributed on a high performance multiprocessor bus and method therefor

Abstract: A distributed error correction circuit for a synchronous high performance multiprocessor bus wherein the memory directly transfers data containing error fields to the multiprocessor bus without performing an error check. Each device, such as a plurality of processors or input/output busses, connected to the multiprocessor bus has error correction circuitry located between the multiprocessor bus and the device to perform error correction while the data is being transferred off the multiprocessor bus and stored in data buffers at the bandwidth of the multiprocessor bus. The error correction circuit detects and corrects data errors caused by the memory or the multiprocessor bus. The stored data is later transferred out of the buffers at the bandwidth of the device. Data from a device is delivered into the device buffers at the bandwidth of the device for later delivery of the data into memory at the bandwidth of the multiprocessor bus. During such transfers, the error correction circuitry generates the error field as the device data is transferred onto the multiprocessor bus.

System for controlling multiple line cards on a TDM bus

Abstract: In a TDM telecommunications terminal, wherein multiple line cards are connected to a TDM bus, each line card location is provided with an identification code. A processor controlled circuit generates a programmable sequence of identification codes which are transmitted on a configuration bus in time slots synchronized with the time slots of the TDM bus. The configuration bus is connected to each of the line cards, which include a comparator logic circuit for comparing the identification of the line card location to the identification codes provided on the configuration bus. When a match is detected, the line card is enabled and is given access to the TDM bus. Through the programmable reassignment of time slots to line cards, concentration may be provided by the system, and a plurality of time slots may be assigned to a single line card to provide broad band service.

Backplane bus system including a plurality of nodes

Abstract: A system for communicating between a plurality of nodes in a computer, each node including logic circuitry for transmitting and receiving data. The subject system includes (1) a backplane bus for carrying the data between the nodes, (2) a driver in each node and a current source circuit coupled to the bus which drive the bus in parallel to decrease the transition time of the data transmitted onto the bus, and (3) coupling resistors individually coupling the bus to the driver in each node and providing impedance matching between the bus and nodes and permitting driver overlap at the bus so that the higher speed and lower power dissipation occurs. In the preferred embodiment, CMOS logic circuitry is utilized and resistors are used to terminate the ends of the bus to the supply voltages.

Data communication interface integrated circuit with data-echoing and non-echoing communication modes

Abstract: An integrated circuit communication interface device includes data bus terminals, a serial output terminal, a serial input terminal, and an internal data bus. A data bus buffer connects the data bus terminals to the internal data bus. A transmit buffer connects the serial output terminal to the internal data bus. A receive buffer connects the serial input terminal to the internal data bus. Control circuitry controls the buffer so that the device receives or transmits data in either the Echoplex protocol or the RS 232 protocol. The device includes a data register which is programmed to select the device's mode of operation.

Packet communication system and its control method

Abstract: A packet communication system suitable for a high speed bus, and a method of controlling the system. A data bus is divided into a control bus for receiving data for contention control and a transmission bus for receiving only communication data including destination data. Each terminal interface transmits the contention control data to the control bus in the transmission cycle prior to transmission of its packet to perform contention control. Thus, exclusive occupation authority of the transfer bus is acquired prior to packet transmission. Each terminal interface finishes the contention control in the cycle prior to the data transmission cycle to previously make a reservation for the use of the bus, and outputs the packet following the DLA onto the transmission bus in the next data transmission cycle.

System for controlling data bus communications of a data bus for vehicles

Abstract: A data bus system for vehicles in which the various subsystems communicate with one another via a common data bus is provided in which the subsystems are in each case connected with the data bus via a station. The stations have registers for the storage of data required and furnished by the corresponding connected user. These stations, for the reception of the data required by the corresponding subsystem, are continuously connected to the data bus, while the stations for the sequential transmitting of the data furnished by the corresponding subsystem are sequentially connected to the data bus for a time interval equaling the length of the data to be transmitted.

Bus device for generating and responding to slave response codes

Abstract: A bus device of a first type is designed to work with a bus devices of a second type. A bus device of the second type, when it is a slave in a bus transaction, issues an ACK if it can respond to the command on time, a NO ACK if it can't respond at all, a STALL if it expects to be able to respond with only a short delay, and a RETRY if it expects to be able to respond, but only after a long delay. Slave Bus devices of the second type also monitor the length of time that they assert the STALL signal, and if they assert if for more than a predetermined period, they replace the STALL signal with a RETRY. Bus devices of the second type, when they are master in a bus transaction, respond to a NO ACK by terminating a transaction in one way and to a RETRY by terminating the transaction in a different way. The bus devices of the first type provided by the present invention, although they are designed for use in conjunction with the second type bus devices, have no means for replacing a STALL with a RETRY when they are slaves in a bus transaction, and no means for responding to a NO ACK and a RETRY by terminating a transaction in a different manner when they are masters in a bus transaction.

Control system for a numerically controlled machine

Abstract: A control system is proposed which is integrated in a single housing and is designed for a numerically controlled machine. The control system comprises a PC board which includes an input device, a processor, a memory, and a PC bus; a plurality of CNC boards, each including a processor, a memory, and a CNC bus; a common control-system bus connected to the CNC bus of each CNC board; and a PC matching circuit provided between the control-system bus and the PC bus. The matching circuit includes a read-write memory, an address multiplexer, a bidirectional data multiplexer, and a control circuit, which depending on the control signals on the control lines of the control-system bus and the PC bus, drives the address multiplexer, the bi-directional data multiplexer, and the read-write memory such that by the control-system bus and also by the PC bus, data can be written into and read out from the read-write memory under desired addresses.

Parallel processing system having a broadcast, result, and instruction bus for transmitting, receiving and controlling the computation of data

Abstract: A computer system utilizes a parallel data broadcast architecture, called "PDB" is adapted to be connected to a host computer system. In one digital embodiment, the PDB system includes an interface and global memory which is connected to the host computer system and to three common buses. The buses, in parallel, are, respectively, a data broadcast bus, an instruction bus and an output bus, each bus being connected to a plurality of computational units. Each computational unit includes an arithmetic processor, which preferably, in this embodiment, is a digital signal processor (a special-purpose integrated circuit microprocessor), a local memory and a local program memory. The computational units receive the input data simultaneously and in parallel; transform the data, depending on the parameters received from the instruction bus; and communicate their results, by multiplexing, to the output bus.