Showing papers on "Bus network published in 1990"

Multi-master bus arbitration system in which the address and data lines of the bus may be separately granted to individual masters

Abstract: A multi-master digital computer system has a bus, a plurality of master devices connected to the bus, a plurality of slave devices connected to the bus, and a bus controller for arbitrating bus requests by the master devices and for granting the bus to a selected one of the plurality of the master devices. Each master device is capable of originating a bus cycle to transmit data to or receive data from a desired slave device. The bus controller grants the bus to a selected master device which enters an address master state and addresses the desired slave device. The selected master device is transferred to a bus master state where a data transfer to or from the slave device is initiated. The selected master device then transfers to a data master state unless the selected master device wants, and is permitted through an arbiter, to retain control of the bus. The bus controller grants a bus request to a requesting master device through to the arbiter. The requesting master device is transferred into the address master state while the selected master device is still in the data master state, thus performing a pipelining operation.

Processor communication bus

Abstract: In a computer system that contains plural computer resource elements, such as multiple processor and memory units, with those elements communicating digital information over a common communications bus, high communications bus efficiency is achieved. An interface permits each of said processor and memory elements to individually and independently access either the data bus, without busying the address bus, or the address bus without busying the data bus, with bus access being limited to a fixed interval of time. Different ones of said processor and memory units may thus simultaneously transfer digital information over the respective address and data bus. The foregoing system includes a bus contention and priority protocol to eliminate the possibility of data collision and includes identification lines for identifying each processor element accessing the bus.

Integrated backplane interconnection architecture

Abstract: A backplane, provides a physical layer level interconnection between a plurality of modules. The backplane includes a physical layer inplementation of an interconnection topology incorporated within one or more integrated circuits called interconnect chips. Incorporated on the interconnect chips are interconnect drivers and interconnect receivers for the physical layer implementation of the interconnection topology. These interconnect drivers and interconnect receivers provide point-to-point links between the physical layer implementation of the interconnection topology and the plurality of modules. Each point-to-point link may include two separate point-to-point link lines, one for an interconnect driver and one for an interconnect receiver. For the bus interconnection topology, alternately, each point-to-point link may be tri-level, including only a single point-to-point link line. The interconnection topology may be, for example, a bus topology, a ring topology or a circuit switched topology.

Arrangement for reserving and allocating a plurality of competing demands for an ordered bus communications network

Abstract: A method and system for allocating a constrained common resource (such as capacity in an ordered bus network) among a plurality of demands for the resource. The allocation arrangement receives from a source, demands for allocating the resource (network) for a particular use, e.g., a conference among a plurality of customer sites, stratifies the received demands in response to a grouping of endpoints to be conferenced at the customer sites, and allocates the network resources to connect the endpoints to be conferenced in response to the stratified demand. This is done by generating setup and terminate times for each endpoint to be connected in a conference; reserving the endpoints to be connected in the conference; and generating a plurality of bindings for signalling the network and the source as to the success of connecting the endpoints to be conferenced over the ordered bus network. The arrangement also stratifies a customer's demand into sets of strategies for groupings of like endpoints; allocates network resources responsive to characteristics of the different groupings of like endpoints; for each strategy, generates the setup times and terminate times for each endpoint, reserves the endpoints for a reservation, and generates bindings. The endpoints may be codecs, alternate accesses, offnets, audio bridges, and/or video conference controllers.

Io adapter for system and io buses having different protocols and speeds

Abstract: A bi-directional bus adapter coupling a system bus, which operates at a first speed using a first protocol, and an IO bus, which operates at a second speed using a second protocol, and allowing data transfering devices on either bus to transfer data to or from devices on the other bus. The bus adapter includes a cycle generation mechanism which is responsive to data cycles from one of the buses in order to generate bus cycles needed to complete a data transfer to a device on the other bus. The bus adapter includes a synchronization mechanism for converting the plurality of data cycles generated by the cycle generation mechanism from either the first speed to the second speed or vice versa. The bus adapter includes bi-directional data path mechanism for routing data between the system and IO buses according to said protocols, such that the data path directs bytes of data to specific data lines to perform byte steering and dynamic bus sizing on the data from the system bus to the IO bus. The bus adapter also includes a bi-directional address transceiver mechanism for routing addresses between said system and said IO buses.

Apparatus and method for assigning addresses to scsi supported peripheral devices

Abstract: Apparatus for assigning addresses to devices connected to an SCSI bus (10). A second configure bus (15) interconnects address assignable devices on the SCSI bus. The assignable devices may be used in a mixed system where some devices have fixed non-assignable addresses. The master device in the SCSI bus transmits configuration commands over the configuration bus and addresses for assignment over the SCSI bus. Acknowledgements are received back from a device which has accepted an address. Once configured with an address, the device propagates subsequent configuration commands to an adjacent device.

Segmented neural network with daisy chain control

Abstract: The present invention is a direct digitally implemented network system in which neural nodes 24, 26 and 28 which output to the same destination node 22 in the network share the same channel 30. If a set of nodes does not output any data to any node to which a second set of nodes outputs data (the two sets of nodes to not overlap or intersect), the two sets of nodes are independent and do not share a channel and have separate channels 120 and 122. The network is configured as parallel operating non-intersecting segments or independent sets where each segment has a segment communication channel or bus 30. Each node in the independent set or segment is sequentially activated to produce an output by a daisy chain control signal. The outputs are thereby time division multiplexed over the channel 30 to the destination node 22. The nodes are implemented on integrated circuits 158 with multiple nodes per circuit. The outputs of the nodes on the circuits in a segment are connected to the segment channel. Each node includes a memory array 136 that stores the weights applied to each input via a multiplier 152. The multiplied inputs are accumulated and applied to a lookup table 132 that performs any threshold comparison operation. The output of the lookup table 134 is placed on a common bus serving as the channel for the independent set of nodes by a tristate driver 44 controlled by the daisy chain control signal.

Data transfer using bus address lines

Abstract: A computer system can transfer data between a master subsystem and a slave subsystem on bus address lines as well as bus data lines during a high speed data transfer. Data is clocked during the high speed transfer by a high speed clock signal which is separate from a normal bus clock signal. Data is transferred at the maximum rate which can be handled by both the master subsystem and the slave subsystem.

Controller for disabling a data bus

Abstract: A software controlled system having a signal source connected to logic circuits via data busses. User operated circuitry permits any selected data bus to be temporarily isolated from the signal source so that maintenance and/or logic circuit replacement may be performed on the isolated data bus.

Method and apparatus for limiting the utilization of an asynchronous bus with distributed controlled access

Abstract: A plurality of units which are coupled to transfer requests, transfer data over an asynchronous bus network during allocated bus transfer cycles. The network has a tie-breaking bus priority network which is distributed to a common interface portion of each of the plurality of units and grants bus cycles and resolves simultaneous requests on a priority basis. At least one unit includes bus saturation detection apparatus included within its common interface portion for monitoring bus activity over established intervals of time. The detection of the occurrence of at least one available cycle over the given interval of time signals that the bus network is not in a saturated state. When the indicator specifies that the bus network is saturated, the unit throttles down its operation by increasing the amount of time between issuing data requests. Throttling continues until the bus is no longer being saturated.

Single bus graphics data processing pipeline with decentralized bus arbitration

Abstract: Stages of a graphics data processing pipeline are interconnected by a common bus for conveying data and arbitration signals to and from each stage. Each data transmitting stage arbitrates for and acquires control of the bus when it has output data to transmit to an addressable storage location within a next stage. Each pipeline stage other than a first stage generates a BUSY bit indicating whether it is processing data or awaiting new input data from its preceding stage. When one pipeline stage has output data to transmit to a next pipeline stage, the transmitting stage periodically polls the receiving stage by acquiring control of the bus and placing on the bus a particular address associated with the next stage. Whenever the next stage detects the presence of the particular address on the bus, it places its BUSY bit on the data lines of the bus. When the sending stage determines from the state of the BUSY bit that the next stage is ready to receive input data, the sending stage acquires control of the bus and sends the input data thereon to the next stage.

DQDB-an access delay analysis

Abstract: The distributed queue dual bus is a protocol being considered by the IEEE 802.6 Working Committee for adoption as a metropolitan area network standard. Its primary function is to interconnect LANs over a high-speed physical medium (optical networks) operating at over 100 Mb/s and to support integrated traffic. Although DQDB is a totally distributed and contention-free protocol with throughput very close to one, the access delays experienced by stations vary with their position on the bus, upstream stations on a particular bus experiencing lesser delays compared to downstream stations. The results of simulation runs that compare the access delays experienced by MAC (media access control) stations at different utilization levels and at different priority levels are presented. It is noted that skewing in access delays is experienced by downstream stations. >

Device controller with a separate command path between a host and the device and a separate data path including a first in, first out memory between the host and the device

Abstract: A SCSI bus controller which has a separate data path from the SCSI bus to the host bus and a separate command path for use to communicate with a local microprocessor The local microprocessor is connected to a dual port RAM, the other port of which is connected to a bus master controller linked to the host system Commands and status are passed via the dual port RAM Data is passed through a FIFO The local microprocessor does not have access to the data path but only controls direction of the data flow, the initiation of the sequence and the completion of the sequence

Portable semiconductor memory device

Abstract: A portable semiconductor memory device includes an internal memory for storing data, an address bus, a control bus, and a data bus which are connected to the internal memory, a connector for electrically connecting the address bus, the control bus, and the data bus to terminal equipment, and a contact confirmation/control circuit which is connected to the address bus, the control bus, and the data bus and in which known data is previously stored and which outputs the known data to the data bus when a read control signal is input from the terminal equipment over the control bus and when a given address is specified on the address bus to indicate the proper connection of the memory device to the terminal equipment through the connector.

Access control method for dqdb network

Abstract: A distributed queue dual bus (DQDB) network has two, oppositely-directed, unidirectional busses. A node with data to send on one bus, can request access to that bus, by sending a bus request signal to all nodes upstream on the bus. The bus request signal is sent to the nodes as part of the traffic flowing on the second bus. Each node counts the number of successive bus request signals transported on the second bus. In a multiple priority system, multiple counts are maintained, one for each priority level. When a given or local node detects an idle slot on the first node, it may write data into that slot if there are no pending downstream access requests of higher priority and if the local node has allowed enough idle slots to pass since its last write operation to service access requests existing at the time of that operation at the same or higher priority levels.

Multiprocessor bus locking system with a winning processor broadcasting an ownership signal causing all processors to halt their requests

Abstract: A method and apparatus for granting, to a select processor in a multiprocessor computing system, exclusive access to a bus for issuance of address, data and command signals thereover, wherein each processor includes bus lock request and bus lock assert elements which provide corresponding bus request and bus hold signals which are recognized by corresponding elements included in other processors connected to the bus. The bus lock according to the present invention assures the processor having lock status of privacy on the bus necessary to complete a specified operation without interruption from the other processors.

Multi-channel/multi-circuit communication controller

Abstract: An ISDN communication controller or a multi-circuit communication controller is implemented in a sheet of communication adapter board. For each channel or circuit, a dedicated subprocessor section conducts communication processing. In each subprocessor section, a local bus is disposed to connect a CPU, a serial controller, and an RAM. In a main processor section controlling the subprocessors, a local bus is employed to connect a CPU, an RAM, and an ROM. In a system processor section exclusively achieving information processing, a system bus is used to connect a CPU and a main memory. The local buses are connected via respective controllers to an upper-level local bus. A shared RAM is connected via a controller to the upper-level local bus and the system bus. The controllers of the subprocessor sections translate addresses to be outputted from the main processor section to the upper-level local bus to supply translated addresses to the respective local bus.

Bus controller with different microprocessor and bus clocks and emulation of different microprocessor command sequences

Abstract: The present invention provides a system whereby the microprocessor and the bus controller in a personal computer can be driven at different frequencies. Furthermore with the present invention the COMMAND DELAY and the WAIT STATE signals on the bus can be adjusted under program control.

Method and apparatus for clock and data delivery on a bus

Abstract: A bus termination scheme that minimizes signal reflection and that minimizes the effect of the number of devices coupled to the bus. In this invention, a resistor is provided between a signal driver and the transmission bus. In addition, a resistance is provided between the bus and each receiving means. The driver resistor reduces the effective capacitance of the transmission line as well as effectively source terminating the line. The receiver resistor reduces effective capacitance and damps signal reflections. Thus, the performance of the bus is increased by minimizing the effects of the number of drivers and receivers on the bus. In addition, the drivers can be lower powered than prior art drivers because no static and a reduced dynamic load is presented to the driver. Finally, the resistors do not dissipate power continuously but only when a transmitter changes the bus state or potential, further enhancing low power operation. The present invention also provides a method for providing a clock signal from any signal source coupled to the bus. In a data transfer transaction, the present invention utilizes a protocol that permits the transfer of two data words with only a single acknowledgement so that the data rate is decoupled from the control signal rate. This permits data to be transmitted at a double word rate even though control signals are provided at a lower rate.

Robot bus architecture with distributed electronics

Abstract: In a multi-jointed robot, position controllers are located at each of the joints of the robot and are interconnected by a unitary bus. The bus carries a loosely-regulated voltage to all of the controllers and also includes data conductors connected to the controllers for disseminating position commands which are time-division multiplexed.

Repeater-switch for distributed arbitration digital data buses

Abstract: The technical field of the invention generally concerns digital computers and, in particular, repeaters or switches (40) for distributed arbitration digital data buses (52, 54, 56, and 58) to which devices (62, 64, 66, 68, 72 and 74) connect in parallel. The bus repeater/switch (40) includes a plurality of bus interface cards (48) that are connected to the distributed arbitration buses (52, 54, 56 and 58) for receiving signals from and transmitting signals to devices (62, 64, 66, 68, 72 and 74) connected thereto. The bus interface cards (48) connect to a control card (44) which allows signals from one of the sharing buses (52, 54 or 56) to be exchanged with the shared bus (58). The bus switch (40) also includes selector switch (84 or 88) for choosing which particular one of the sharing buses (52, 54 or 56) exchanges digital data signals with the shared bus (58). The bus switch (40) responds to signals on the distributed arbitration buses (52, 54, 56 and 58) and to phases of the protocol for those signals so that its presence between pairs of buses (52-58, 54-58 or 56-58) is imperceptible to devices (62, 64, 66, 68, 72 and 74) connected thereto.

Clocked logic circuitry preventing double driving on shared data bus

Abstract: A system wherein multiple sources of data each have drivers for transmitting data to a common system bus. The drivers are each managed by individual enabling logic which is controlled by a flip-flop driven by a clock. Thus no driver can connect and drive data onto the bus until one clock period after the previously connected driver has been disabled and disconnected from the bus.

Bus control circuit for latching and maintaining data independently of timing event on the bus until new data is driven onto

Abstract: In a means and method for optimizing bus utilization with traditional computer system components, one or more latch circuits are coupled to a computer data bus. The latch circuits latch data states on the data bus after the bus has been driven to a desired state by a system driver node. Tri-state drivers are preferred. Once a data state has been latched, the associated driver may be disabled without affecting the data state on the bus. The data state may then be sampled at any time, and the integrity of the data state is preserved, until a new data state is driven onto the bus by a driver node. The latch circuit parameters allow any system driver to readily overcome the latch action, yet preserve the driven data state as logically valid until it is overwritten. Data sampling from the bus is restricted solely during driver enable periods. Bus utilization is optimized without undue sacrifices in system power requirements.

Circuit for testing internal data bus of integrated circuit

Abstract: An internal bus test circuit for testing an integrated circuit internal bus which interconnects a plurality of function modules of the integrated circuit, the test circuit including switches that are operable for isolating respective modules from the bus, a bus setting circuit enabling individual lines to the bus to be set to a desired logic level, and a by-pass bus with corresponding by-pass circuits, for a function module that is connected between the bus and external pads. The test circuit thereby enables the bus functions to be easily tested in real-time operation, independently of the respective conditions of the test modules that are connected to the bus.

Data transfer operations between two asynchronous buses

Abstract: A technique for permitting data transfers between a high speed bus and a low speed bus which operate independently and asynchronously wherein when the low speed bus requires access to the high speed bus, the busy status of the latter bus is determined and transfers are made to the high speed bus at high speed when such bus is not busy. When the high speed bus requires access to the low speed bus, if the low speed bus is busy the requesting master on the high speed bus is temporarily placed in a pending status and is removed from its tenure on the high speed bus, so that the high speed bus is free to handle other requests. When the low speed bus is free, the highest priority pending requestor is provided access to the low speed bus on a priority basis over all then current requestors.

Computer system using multidimensional addressing between multiple processors having independently addressable internal memory for efficient reordering and redistribution of data arrays between the processors

Abstract: A computer system includes sixteen data processors each connected to a communication bus. The communication bus comprises a data bus for carrying data, and an address bus for carrying associated labelling information uniquely identifying the data. Each processor includes read and write detectors connected to the address bus for detecting labelling information of data required by, or presently stored in, respectively, the data processor. A bulk memory having similar read and write detectors is connected to the communication bus. An address generator supplies labelling addresses to the address bus. For each address, one processor or the bulk memory supplies the corresponding data to the data bus, and other processors and/or the bulk memory requiring the data read the data from the data bus. Data is transferred between processors and/or the bulk memory in this way. The address bus and the read and write decoders are configured for multi-dimensional addressing.

Token associated data network communications protocol

Abstract: A multinodal bus network protocol used in communication systems employing tokens to indicate the next interface unit to transmit, with cojoining of token addressing and data in one trasmission, organization of interface units into logical rings whose token-passing sequence is a function of network topology, adaptive learning by each interface unit of the next unit to receive the token as well as the number of addressees in the ring, organization of interface units into groups where only one unit may answer for the entire group, and adaptive learning by each unit in a group of its predecessor in that group as well as the number of units in its group.

Host bus video interface in personal computers

Abstract: A system and method for interfacing a video subsystem (110) capable of driving a video display monitor to a personal computer (PC) architecture. The system and method involves connecting the video subsystem (110) to a host bus (104) via a host bus video interface (402). The host bus (104) communicates directly to a central processing unit (CPU) (102) and to a slower system bus (138) through buffers (124, 128). The central processing unit (102) as well as a system bus master (108) connected to the system bus (138) can communicate at high speeds to the video subsystem (110). The host bus video interface (402) includes a fast temporary storage buffer (406) so that the CPU (102) or the system bus master (108), during a write cycle to the video subsystem (110), can write data at high speed to the video subsystem (110). The video subsystem (110) may further include SRAM in its video memory (422) to increase performance.

Host interface design for experimental, very high-speed networks

Abstract: A critical bottleneck in very high-speed networks is the interface between host computers and the network. Some of the fundamental problems of designing such an interface to make full use of the available network bandwidth are examined. These problems are those which are independent of the nature of the underlying network and those which depend on the network. The most notable problem is the limitations of current bus bandwidths. An architecture is proposed to minimize the effects of this limitation and with the aim of providing higher speeds as bus bandwidths increase. The proposed interface consists of a network-independent part, which performs transport-level functions, and a network-dependent part, which deals with the units of multiplexing that are handled by the network. Although it is believed that the former can be (mostly) implemented by an off-the-shelf processor, the latter is likely to require a substantial amount of dedicated hardware. The requirements for this hardware and possible implementation are described. >