Showing papers on "Bus network published in 1991"

Integrated circuit I/O using a high performance bus interface

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices (15, 16 , 17), including at least one memory device (15, 16 or 17), connected to a bus (18), where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices (15, 16 or 17), where the control information includes device-select information and the bus (18) has substantially fewer bus lines than the number of bits in a single address, and the bus (18) carries device-select information without the need for separated device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus (18) and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices (15, 16, 17). The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an Address Valid bus line carry address, data and control information for memory addresses up to 40 bits wide.

Multiprocessor system having local write cache within each data processor node

Abstract: A multiprocessor data processing system (10), and a method of operating same, so as to provide efficient bandwidth utilization of shared system resources (24, 26). The system includes a plurality of processor nodes, each of which includes a data processor (22a, 28a). A first step of a method buffers data written by a data processor to a first bus (23a), prior to the data being transmitted to a second bus (32). Also buffered are byte enable (BE) signals generated by the data processor in conjunction with the data written by the data processor. A next step performs a main memory (26) write operation by transmitting the buffered data to the second bus; responsive to the stored BE signals, also transmitting a control signal for indicating if a memory write is to be accomplished as a read-modify-write (RMW) type of memory operation; and transmitting the stored BE signals to the second bus. A further step couples the data, the RMW signal, and the BE signals from the second bus to a third bus (24) for reception by the main memory.

Cache memory and bus width control circuit for selectively coupling peripheral devices

Abstract: A bus width control circuit being arranged between a first bus and a second bus both of n-bits width, and comprising a buffer group being connected to the first bus and which split data of n-bits into partial data of m-bits and buffer them, a selector which connects each buffer to the second bus in parallel in the case where the effective data bus width of the second bus is n bits and which connects each buffer to a predetermined m bits of the second bus in the case where the effective data bus width of the second bus is m bits, and a control circuits thereof, and a control circuit which locates intact the n-bits data of the first bus in the second bus or by splitting it into partial data of m-bits in a predetermined portion of n-bits data and outputs them sequentially to the second bus, or which splits the n-bits data of the second bus into partial data of m-bits and buffers them in each buffer and then simultaneously outputs them to the first bus, or which sequentially buffers data whose m bits alone of the second bus is effective into each buffer and then simultaneously outputs them to the first bus.

A 40-ns 64-Mb DRAM with 64-b parallel data bus architecture

Abstract: The authors describe circuit techniques for wide input/output (I/O) data path and high-speed 64-Mb dynamic RAMs (DRAMs). A hierarchical data bus structure using double-level metallization has been developed to form 64-b parallel data bus lines without increasing the chip size. A current-sensing data bus amplifier, developed to sense the 64-b data bus signal in parallel, has made the wide I/O data path structure possible. A direct-sensing type column gate circuit with the READ/WRITE separated select line scheme achieves 40-ns RAS access. A shielded bit-line three-dimensional stacked-capacitor cell with a double-fin storage capacitor stores sufficient charge while the bit-line capacitance shows a reasonable value for sensing the data. >

Apparatus and method for a synchronous, high speed, packet-switched bus

Abstract: A high speed, synchronous, packet-switched inter-chip bus apparatus and method for transferring data between multiple system buses and a cache controller. In the preferred embodiment, the bus connects a cache controller client within the external cache of a processor to a plurality of bus watcher clients, each of which is coupled to a separate system bus. The bus allows the cache controller to provide independent processor-side access to the cache and allows the bus watchers to handle functions related to bus-snooping. An arbiter is employed to allow the bus to be multiplexed between the bus watchers and cache controller . Flow control mechanisms are also employed to ensure that queues receiving packets or arbitration requests over the bus never overflow. A default grantee mechanism is employed to minimize the arbitration latency due to a request for the bus when the bus is idle.

Method and apparatus for memory access in a matrix processor computer

Abstract: A matrix processor comprises a system with a variable number of buses, each bus having a variable number of processing elements which may operate in parallel. Each bus accesses a port into a memory crossbar and a multiport memory system also accesses crossbar ports. Efficient sharing of bus accesses by processors and synchronization of processors on each bus is accomplished via registers located on the buses, which may be read and written by processors. Interbus synchronization is also accomplished via register accesses. The matrix processor may be configured as a coprocessor or as a stand alone device. A method of synchronizing the processors and buses, performed by at least one processor on at least one bus, includes reading a barrier state of the processors, synchronizing the processing elements on a each bus, reading the barrier state of the buses, and synchronizing each bus.

Resource allocation in a dynamically partitionable bus network using a graph coloring algorithm

Abstract: An efficient dynamic graph traversal algorithm is used to identify nonconflicting requests and to allocate network resources in a dynamically partitionable bus network (DPBN). In centralized network control a special processor receives from the control computer of a partitionable bus network an adjacency matrix which indicates conflicts among requests. It applies the dynamic graph traversal algorithm and returns the identified nonconflicting requests to the control computer. The control computer then physically partitions the network into a number of subnetworks for processing the nonconflicting requests in parallel. In distributed control, each station determines conflicts and sets the switches. The results of performance evaluation show a 40% decrease of network delay as compared with a fully utilized, but unpartitioned local area network. >

Register bus multiprocessor system with shift

Abstract: A digital data processing apparatus includes a shift-register bus that transfers packets of digital information. The bus has a plurality of digital storage and transfer stages connected in series in a ring configuration. A plurality of processing cells, each including at least a memory element, are connected in a ring configuration through the bus, with each cell being in communication with an associated subset of stages of the bus. At least one processing cell includes a cell interconnect that performs at least one of modifying, extracting, replicating and transferring a packet based on an association, if any, between a datum identified in that packet and one or more data stored in said associated memory element. The cell interconnect responds to applied digital clock cycle signals for simultaneously transferring at least a selected packet through successive stages of the bus at a rate responsive to the digital clock cycle rate, while performing the modifying, extracting, replicating and transferring operation.

Real-time communications in a computer-controlled workcell

Abstract: A computer-integrated manufacturing (CIM) system is composed of several workcells, each of which contains robots, numerical-control machines, sensors, and a transport mechanism. The author considers a communication subsystem that is designed to support real-time control and coordination of devices in each CIM cell. The concept of a poll number is proposed to control the access to the intracell bus. The bus access mechanism with the poll number is intended to minimize the probability of real-time messages missing their deadlines. Use of a poll number provides not only for decentralized control of the intracell bus, but also a high degree of flexibility in scheduling messages. The performance of the bus access mechanism with a poll number is analyzed and compared with that of a token bus which is widely used in CIM systems such as MAP (Manufacturing Automation Protocol) networks. The probability of a real-time message missing its deadline in a token bus is found to be much higher than that of the proposed mechanism. >

Activity monitor system non-obtrusive statistical monitoring of operations on a shared bus of a multiprocessor system

Abstract: An activity monitor for monitoring activity on a bus connecting a plurality of processors, monitors the bus to determine the bus master and other bus activities. In response thereto, predetermined memory locations are enabled to count events on the bus or calculate time spans for various bus activities.

Centralized backplane bus arbiter for multiprocessor systems

Abstract: An Arbiter (36) is coupled to a multiprocessor system (10) Global Bus (24) having two separate main buses: an address bus (ABUS) and a data bus (DBUS) Bus agents coupled to the Global Bus request access to use the buses by asserting bus request lines to the Arbiter The Arbiter is a dual level, round robin Arbiter that employs a fast, single-cycle arbitration technique During each system clock cycle, the Arbiter considers the signals on the request input lines and generates corresponding grant output lines which dictate, for the next cycle, which bus agent is to receive access to the address bus and which bus agent is to receive access to the data bus

Bus arbitration system for granting bus access to devices following two-wire bus arbitration protocol and devices following three-wire bus arbitration protocol

Abstract: A bus arbitration system is capable of granting access to an expansion bus to devices following two-wire bus arbitration protocol or a three-wire bus arbitration protocol. The bus arbitration system receives a plurality of bus request signals from a plurality of devices. Each bus request signal is made up of one or more coded pulses and has a predetermined priority. A priority encoder receives the bus request signal and assigns a priority level to each bus request signal. An arbiter determines and stores in memory which bus request signal has a highest priority and whether the device follows two-wire bus arbitration protocol or a three-wire bus arbitration protocol. The expansion bus grants access to the bus to the device having the highest priority once a previous device if any, has relinquished the bus.

Control system network structure

Abstract: The present invention imports network communication concepts into a motor and/or motion control system. The motor and/or motion control system is divided into various modules. A preferred configuration includes a motor drive control module, a user command module, and a master control module. The modules are interconnected by a simple hardware bus, such as an RS-485 bus. Communication between the modules is accomplished using a time division protocol.

Multi-segmented bus and method of operation

Abstract: A multi-level hierarchical bus architecture implemented with a multi-chip package and a modular shared-bus provides high bandwidth. All IC components are mounted on standardized multi-chip packages. Each multi-chip package includes bus interface chips for providing communication from the integrated circuits to a board bus. One multi-chip package contains additional bus interface circuitry for providing communication from the board bus to a backplane bus.

Bi-directional bus repeater

Abstract: A bi-directional bus repeater includes two unidirectional bus repeaters connected for retransmitting signals in opposite directions between two buses. When an external bus driver pulls either bus low, one of the unidirectional bus repeaters pulls the other bus low. When the external bus driver allows the bus to rise to the high logic level, the unidirectional bus repeater temporarily supplies a high charging current to the other bus to quickly pull it up. Each unidirectional bus repeater also generates signals indicating when it is actively pulling its output bus up or down and the indicating signals inhibit one unidirectional bus repeater from actively driving its output when the other unidirectional bus repeater is actively driving its output.

Integrated circuit logic functions simulator for selectively connected series of preprogrammed PLA devices using generated sequence of address signals being provided between simulated clock cycles

Abstract: A hardware simulator comprises a plurality of interconnected programmable logic devices (20) which are connected via a data bus (22) and a control bus (24). Address signals on control bus (24) are read by an interconnect logic block (18) associated with each device to selectively link the output latches and input latches of the devices (20) to the data bus (22). Accordingly, a series of signal transfers is carried out between the devices simulating the hardware. The interconnect logic blocks may be programmed to provide whatever connections between devices are required.

Coherent detection loop distribution system

Abstract: An optical fiber point-to-multipoint communications network is disclosed of the type having a bus topology. The broadcasting terminal (101) of the network includes an information transmitting laser (102) and a local oscillator laser (103) the signals of which are launched onto opposite ends of an optical fiber bus (104) to counter-propagate thereon. At each of the M stations (105-1-105-M) connected to the bus, a wideband directional coupler (106-1-106-M) couples portions of each of the counter-propagating signals to a balanced coherent detector (107-1-107-M). The effective total power input to the balanced coherent detector at each of the stations is equal regardless of the location of the station relative to the broadcasting terminal. In another embodiment the stations are connected to ring-shaped optical subbuses which are coupled to the main bus. Several two-way point-to-multipoint embodiments are disclosed which employ wavelength division multiplexing techniques to enable communications from the stations back to the broadcasting terminal.

Dynamic switch protocols on a shared medium network

Abstract: Dynamic switch protocols are implemented on a token bus protocol in a shared medium network to improve the basic token bus functional capabilities and link utilization, and to produce a uniform transaction protocol that supports both token bus and dynamic switch networks. Frame formats common to both token bus and dynamic switch protocols are utilized, and circuit switched protocols are superimposed on a token bus protocol in interlocked and data transmissions to establish a circuit switched path between a token holder sender node and a destination node. An initial frame transmission uses a normal link header and establishes the circuit switched path between the sender node and the destination node. Subsequent data frames contain no link header information, thereby improving transmission efficiency, and the last frame in such a transmission disconnects the switched circuit path, thereby allowing other transmissions to resume. The use of circuit switched protocols within a token bus protocol allows more general transmission sequences and improves the utilization of token bus bandwidth.

Method and apparatus for shared use of a multiplexed address/data signal bus by multiple bus masters

Abstract: A multiplexed address/data signal bus capable of supporting multiple bus masters includes a group of control signal lines "shared" by each bus requestor device (BRD) coupled to the bus and a group of control signal lines "replicated" into sets, one for each BRD. The bus arrangement includes a central arbitration unit located in a host bus interface (HBI) which controls BRD access to the bus. A selection control signal is provided to select a set of replicated control signals corresponding to a current bus master. Bus isolation units (BIUs) are provided to isolate the BRDs from the shared control signals, thereby allowing multiple BRDs to "simultaneously" utilize the signal bus in order to execute multiple bus transactions in parallel.

Bus flow control mechanism

Abstract: The flow of work requests in a server driven process to process communication environment is described Logical connections between processes and bus managers interfacing bus units to an I/O bus are assigned to connection groups for management by the bus managers Each bus unit has its own connection groups for the logical connections Bus unit resources are assigned to each connection group based on performance factors, and a series of bus unit messages are used to control the flow of work so that a group which has no more resources will not accept further work requests The originator of the work requests will resequence rejected work requests and resend them when the connection group has freed up resources A further mechanism is provided to facilitate work consistent with the server driven architecture when bus units do not have adequate DMA capabilities Two ways of reversing control of transfer of work requests and data so that the server need not have master DMA capability are presented Management of storage in a remote processor is used to transfer work and its associated data into storage accessible by a bus unit with slave DMA capability The slave DMA bus unit then transfers the information into storage is manages In another way of reversing the flow, a bus unit message is used to make the original server a requestor The bus unit message contains information which varies the request sent by the requestor In this manner, the server, which was the original requestor transfers information using its master DMA capability flow

Current mode data bus digital communications system

Abstract: A current mode data communication system is disclosed in which the system data bus is formed by an unshielded twisted wire pair (12). Coupled to the data bus by bus couplers (16) and bus-to-stub couplers (80) are current mode data stubs (82), which also are formed by pairs of twisted, unshielded wires (84 and 86). One or more interface-to-stub couplers (88) are inductively coupled to each current mode data stub and, in addition, are connected in signal communication with one of the system utilization devices (10). Data signals propagating along the system data bus (12) are coupled to each utilization device (10) via an associated bus coupler (16), bus-to-stub coupler (80), and interface-to-stub coupler (88) without reflecting the signal into the system data bus (12). Signals are supplied to the system data bus (12) by each utilization device (10) via an associated interface-to-stub coupler (88), current mode data stub (82), bus-to-stub coupler (80) and bus coupler (16) without direct coupling of the signal to either the receive channel of the utilization device (10) that is transmitting signals to the system data bus (12) or the receive channels of other utilization devices (10) that utilize the same current mode data stub.

Data transfer circuit for interfacing two bus systems that operate asynchronously with respect to each other

Abstract: A circuit for transferring data from one bus system to another is disclosed. The circuit allows the write bus to perform write operations indiscriminately of any handshaking, wait states or other control signals which would otherwise reduce the bus efficiency of the system. Similarly, the read bus system has no handshaking or wait states but is provided with a data ready signal to indicate when valid data may be read. This circuit is used in applications where less than 100% data integrity is permissible.

Direct control facility for multiprocessor network

Abstract: Control panel function is provided to bus units coupled together by an I/O bus. At least one bus unit has the capability to issue control commands through the bus to one or more other bus units. A control facility is integrated into bus units, and makes full use of existing paths to processor registers and main storage. Control commands are distinguished from other bus communications, and executed by the control facility, to provide a full control panel function for each bus unit incorporating the control facility.

Bus contention resolution method for network devices on a computer network having network segments connected by an interconnection medium over an extended distance

Abstract: A method is used to perform arbitration between network devices connected to one of a first network segment and a second network segment, where the first network segment is connected to the second network segment by a long interconnection medium over an extended distance. When one or more network devices connected to the first network segment senses the network is free and desires control of the network for a data transfer, each of these network devices will assert a first network control signal. When the first network control signal is first asserted, this marks the beginning of an arbitration period for the first network segment. The first network control signal is forwarded to the second network segment. Upon the second network segment receiving the first network control signal, any arbitration currently in progress upon the second network segment is aborted. Upon completion of the arbitration period and provided arbitration on the first network segment has not been aborted, one of the network devices connected to the first network segment is granted control of the network.

Bus system wherein a bus-using request signal is issued in advance of a determination that a bus is to be used and is thereafter cancelled if the bus is not used

Abstract: A method is provided for controlling bus-using rights in a multi-bus system which has a plurality of buses and a plurality of units connected to each of the buses. A unit connected to one bus is accessible by another unit connected to another bus. When a first unit accesses either a second unit on the one bus or a third unit on another bus, two requests for use of the one and another buses are issued substantially at the same time, thereby reducing the time taken for acquiring a bus-using right of the another bus. As soon as it is found that access is directed to the second unit on the one bus, the request for using the another bus is canceled, thus reducing a bus occupation rate for the another bus.

Address bus control apparatus

Abstract: An address bus control apparatus links a memory bus connected with a CPU and a memory unit and a system bus connected with input/output units. The address bus width of the system bus is smaller than that of the memory bus and one of the input/output units is a master unit using address data of a smaller width than the address bus width of the system bus for accessing another unit. The address bus control apparatus, when bus identifying information from a master unit identifies the memory bus, delivers first complementary address data together with address data from the master unit onto the memory bus and, when the bus identifying information identifies the system bus, delivers second complementary address data onto the system bus, and thereby secures necessary address data width for each bus.

Centralized bus arbitration circuit

Abstract: The centralized bus arbitration circuit 20 shown here allows processor 12-18 access to a bus 10 for a period of time determined by either the processor 12-18 or the circuit 20, as appropriate. Indefinite access and immediate return of control to the bus arbitration circuit 20 are also provided for.

Lock converting bus-to-bus interface system

Abstract: A bus-to-bus interface circuit maps a portion of the address space of each bus to a corresponding portion of the address space of the other bus. When a computer processor one one bus attempts to read or write access a mapped address, the bus interface circuit obtains control of the other bus and read or write accesses a corresponding address on the other bus. The interface circuit permits a bus master on the first bus to lock both buses so that it may perform several bus-to-bus data read or write operations without having to re-arbitrate for control of either bus after each operation.

Personal computer with bus interface controller coupled directly with local processor and input/output data buses and for anticipating memory control changes on arbitration for bus access

Abstract: This invention relates to personal computers, and more particularly to personal computers in which arbitration for control over a data handling bus occurs among a plurality of "master" devices coupled directly to the bus and memory address signals are varied in response to such arbitration. The personal computer system has a high speed local processor data bus, an input/output data bus, a microprocessor coupled directly to the local processor bus, volatile memory coupled to the local processor bus for volatile storage of data, and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the buses. The bus interface controller provides for arbitration among devices directly coupled to the input/output data bus for access to the input/output data bus and to the local processor bus, and for arbitration among the input/output data bus and said microprocessor for access to the local processor bus. The bus interface controller is also coupled to the volatile memory for supplying row address select signals to the volatile memory and thereby selecting data storage areas to be accessed, and responds to a change in access granted to the local bus by changing the row address select signal supplied to the volatile memory in preparation for access to potentially different data storage areas of the volatile memory.

Photonic multihop bus networks

Abstract: The photonic bus network (PBNet) approach to the design of small backbone networks is considered. The basic building block of PBNets consist of a linear multihop network interconnected in a bidirectional bus virtual topology using point-to-point optical channels. The system is designed to exploit transmissive optical star technology employing multichannel coherent lightwave modulation, but a wavelength-division implementation is also possible. The NCounter Protocol is introduced as a way of achieving fair bandwidth allocation in the presence of network overload conditions. Due to the optical implementation, there is considerable flexibility in PBNet topological design and bandwidth deployment. New design algorithms are introduced for this purpose. Performance results show that substantial improvements in system operation are possible using the proposed design techniques. In addition, the concept of receiver allocation is introduced which permits simple performance evolution of fixed-channel PBNets. >