Showing papers on "Bus network published in 1992"

Shared memory bus system for arbitrating access control among contending memory refresh circuits, peripheral controllers, and bus masters

Abstract: An arbitration system for a shared address, data and control bus provides burst mode operations for transferring data between a peripheral device and memory via a bus master. The arbitration system is responsive to high priority bus activities, such as memory refresh cycles and DMA cycles to temporarily transfer control of the shared bus from the bus master to a circuit controlling the high priority activity. After the high priority activity is completed, the arbitration system returns control of the shared bus to the bus master so that the associated peripheral device may continue operating in the burst mode. This transfer of control occurs without requiring the time overhead of arbitrating priority between bus masters having active bus requests. The arbitration system further includes timing circuits to assure that a bus master transferring data in the burst mode does not retain control of the shared bus for an excessive amount of time.

High speed bus system

Abstract: In the high speed bus system of the present invention, the bus configuration is one in which all master devices are clustered at one end of an unterminated end of the bus. The slaves are located along the remaining length of the bus and the opposite end of the transmission line of the bus is terminated. By eliminating the termination resistor at the end of the bus where the master devices are located the required drive current needed to produce a given output swing is reduced. The bus drivers and receivers are CMOS integrated circuits. The bus of the present invention is operable utilizing small swing signals which enable sufficient implementation of current mode drivers for low impedance bus signals. In particular, the bus input receiver of the present invention comprises a two stage buffered sampler/amplifier which receives a small swing signal from the bus and samples and amplifies the low swing signal to a full swing signal within a single clock cycle using CMOS circuits.

Methods and apparatus for bus access arbitration of nodes organized into acyclic directed graph by cyclic token passing and alternatively propagating request to root node and grant signal to the child node

Abstract: A bus arbitration scheme is implemented in a system where an arbitrary assembly of nodes on a system bus have been resolved into an acyclic directed graph The hierarchical arrangement of nodes has one node designated a root while all other nodes have established parent/child relationships with the nodes to which they are linked Each node may have a plurality of connected child ports with a predetermined acknowledgment priority scheme established Fair bus access arbitration provides for bus granting in a sequence corresponding to the predetermined port priorities allowing all nodes a turn on the bus The root node may always assert its priority access status to gain bus access which is useful for accommodating a root node which requires isochronous data transfer Alternatively, a token passing arbitration scheme may be implemented where the token for bus access is passed around the nodes according to the above-described predetermined port priority scheme Preemptive bus initialization may be triggered by any node upon detection of a necessitating error or addition or removal of a connection to an existing node

Bus-oriented switching system for asynchronous transfer mode

Abstract: A local network system is provided using ATM-like framing and cells for data transmission. A bus architecture is defined, making the cost per port relatively low compared to matrix switching. For high performance, the bus is bit parallel instead of being a serial link. Like other LANs, the average bandwidth per interface (per port) is a low percentage of the peak bandwidth. A single physical bus is used to interconnect a potentially large number of ATM interfaces, on the order of hundreds. The system employs a bus master which provides timing and resolves all arbitration requests. Interfaces connected to the bus are allotted at least one cell per frame for sending data, and write to the allotted cell in synchronization with the frame, cell and bit clocks circulated on the bus from the master. There are more cells than interfaces, so when an interface has a large data block to send it asks for allocation of more cells per frame, and the request is granted by the master coordinated with other demands on the system. This bus arrangement allows construction of a switching system providing asynchronous transfer mode (ATM) cell switching with an aggregate throughput defined by the bus transfer speed, potentially in the multi-gigabit range, while also allowing the bus to be used for pre-arbitrated (isochronous) transmission. The bus uses a "traveling wave" technique to allow arbitrary physical length (many times the transit distance of one bus cycle) while using a simple, lower-speed sub-bus for bandwidth arbitration.

Data processor with bus-sizing function

Abstract: A data processor capable of controlling memory accessing by the same controls regardless of the bus width to be used. A register is provided for storing data to be inputted and completing a block of data with a size equal to that of the whole bus width of the external data bus when the microprocessor accesses external memory by using only a part of the bus width of an external data bus according to a bus-sizing function. A bus interface is provided for starting memory access by dividing a bus cycle into plural portions according to the bus width and for controlling operation so as to access data equal in size to the case where the whole bus width of the external data bus is used for accessing.

Method of arbitration for buses operating at different speeds

Abstract: In a bus adapter coupling a system bus and an I/O bus which operate at different speeds and contain a plurality of devices, a method by which an arbiter in the bus adapter prevents contention for ownership of both buses by a device on either of the buses. The method includes the steps of sampling each of the devices requesting ownership of said buses and asserting a bus grant to one of the devices on one of the buses based on its assigned priority number. The method also includes the step of waiting for the device granted the bus to send an acknowledge signal to display ownership of the buses and for each of the devices not on the bus containing the device granted the bus to see the acknowledge signal before resampling and reasserting a new bus grant to another of the requesting devices.

A bus on a diet-the serial bus alternative-an introduction to the P1394 High Performance Serial Bus

Abstract: The author discusses the justifications for the use of a serial bus in computer systems. He then describes a leading proposal for such an interconnect: the IEEE P1394 High Performance Serial Bus. The highlights of the Serial Bus include: (1) a physical layer supporting both cable media and many ANSI/IEEE standard 32-bit buses; (2) variable speed data transmission with a base speed of almost 100 Mbit/sec between nodes separated by distances up to 10 meters; (3) both fair and priority arbitration mechanisms with all nodes guaranteed at least partial access to the bus regardless of priority; (4) bus transactions that include block and single quadlet reads and writes, as well as an isochronous mode which provides a low-overhead guaranteed bandwidth service; and (5) dynamic address assignment that does not require switches or a physical 'slot number'. >

Bus synchronization apparatus and method

Abstract: Several techniques are used to optimize the transmission of signals or events from one bus to the other. In one aspect, the user of a chipset is permitted to choose whether the originating events (i.e. the events in response to which a destination event is to be generated on a destination bus) are to be generated synchronously or asynchronously with the clock signal on the destination bus. Whether synchronous or asynchronous generation is chosen, the chipset may perform a synchronization function in response to an originating bus predictor signal. The number of destination clock cycles to delay before generating the desired destination bus event is responsive to the relative frequencies of the clock signals on the two buses, thereby accommodating a wide variety of such relative frequencies. In another aspect, for events to be generated on a destination bus synchronously with a clock signal which is by specification stretchable, the destination bus event is generated promptly in response to the originating event and then the destination bus clock signal is stretched to make the destination bus event synchronous with the destination bus clock signal. The length of the stretch is responsive to the relative frequencies of the originating bus and destination bus clock frequencies. A synchronizer is used to generate the destination bus event synchronously with the destination bus clock signal. The user of the chipset can select which formula is to be applied.

SCSI interface employing bus extender and auxiliary bus

Abstract: A bus interface employs a bus extender for connecting an auxiliary bus to a single port on a main bus in such a way as to interconnect one or more host computers on the main bus to one or more peripheral devices on the auxiliary bus. The bus extender employs a transceiver coupled to the main bus, another coupled to the auxiliary bus, and signal transfer and logic circuitry passing signals between and controlling the operation of the transceivers. The circuitry also performs all address translation necessary for inter-bus communication. Once communication links have been established with the designated devices on the other bus, the extender sends message data signals received over the one bus directly onto the other bus without modification. Since the interface can comply with SCSI standards, any of a variety of types of commercially available peripheral devices having controllers complying with those standards can be supported on the auxiliary bus.

Computer system with a processor-direct universal bus connector and interchangeable bus translator

Abstract: A universal processor-direct bus structure on a specifically partitioned motherboard uses a separate local bus translator card to adapt to a specific local bus protocol and configuration The processor-direct bus on the motherboard contains a superset of all of the primary signals required to implement any desired local bus structure The translator card incorporates the connectors and bus translation protocol for a specific local bus structure on a separate card which is connected to the partitioned motherboard through the universal processor-direct bus Thus, the universal processor-direct bus combined with the translator card makes it possible to have a standard bus (for example an ISA (Industry Standard Architecture) bus, EISA bus, MCA bus, PCI bus, C-bus, S-100 bus and/or other buses) mounted directly on the motherboard with one or more of the same standard buses or a different local bus interfaced to the motherboard through the universal processor-direct bus This unique combination of a motherboard having a universal processor-direct bus with plug in local bus translator cards provides a unique, low cost, flexible solution to the problem of standard and local bus obsolescence, local bus non-upgradeability and local bus non-flexibility

Communications method for a shared-medium communications method

Abstract: A communications method for a shared-medium communications network having a plurality of stations connected by a first and second bus. The first bus is for data transmission in one direction and the second bus is for data transmission in an opposite direction. The method includes transmitting data between stations in slots. A station desiring to transmit requests the use of a slot by placing a request signal on the bus in a direction opposite to the desired direction of transmission. A slot is then used on a first request, first use priority except for a least one station which is allocated a slot without regard to the first request first use priority. This allocation provides for guaranteed bandwidth traffic.

Method and apparatus for concurrency of bus operations

Abstract: A method and apparatus for performing concurrent operations on the host bus, expansion bus, and local I/O bus as well as the processor bus connecting the processor and cache system to increase computer system efficiency. A plurality of CPU boards are coupled to a host bus which in turn is coupled to an expansion bus through a bus controller. Each CPU board includes a processor connected to a cache system including a cache controller and cache memory. The cache system interfaces to the host bus through address and data buffers controlled by cache interface logic. Distributed system peripheral (DSP) logic comprising various ports, timers, and interrupt controller logic is coupled to the cache system, data buffers, and cache interface logic by a local I/O bus. The computer system supports various areas of concurrent operation, including concurrent local I/O cycles, host bus snoop cycles and CPU requests, as well as concurrent expansion bus reads with snooped host bus cycles.

Method and apparatus for connecting nodes for a computer network

Abstract: The present invention provides a method and apparatus for extending an Ethernet 10Base-T local area network topology from only allowing point-to-point link segments to allowing daisy-chained segments having multiple nodes on each segment. Thus, computer equipment can be connected in a bus topology while retaining the characteristics of a 10Base-T node according to IEEE Standard 802.3 for 10Base-T Ethernet. In the preferred embodiment of the present invention, a non-reclocking repeater at a 10Base-T node retransmits data packets from the node to subsequent nodes in a daisy-chained segment. When the repeater is not powered, bypass circuitry connects the two ends of 10Base-T wiring to remove the inactive node from the daisy-chain segment. The repeater includes modular connectors and analog transmit and receive sections for transmitting and receiving differential signals between two network link interfaces and an AUI. The repeater further comprises digital logic to implement the functional circuitry of a 10Base-T Medium Attachment Unit (MAU). It includes logic to detect data packets having two formats and link pulses. Because the IEEE Standard 802.3 only allows a fixed number of bits to be lost at a 10Base-T node, a repeater retransmits data packets having formats such that nodes further down the segment do not lose additional bits. The present invention also includes diagnostic circuitry including LEDs to aid installation and to provide useful information including collision detection and link integrity.

System for awarding the highest priority to a microprocessor releasing a system bus after aborting a locked cycle upon detecting a locked retry signal

Abstract: Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2)×(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allows a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.

Programmable logic cell and array with bus repeaters

Abstract: A programmable logic array comprising cells and a bus network in which the cells are arranged in a two-dimensional matrix of rows and columns and are interconnected by the bus network. The cells are also interconnected by a two-dimensional array of direct connections between a cell and its four nearest neighbors, one to its left (or to the West), one to its right (or to the East), one above it (or to the North) and one below it (or to the South). Each cell comprises eight inputs, eight outputs, means for multiplexing the eight inputs onto two leads and logic means that operate in response to the signals on the two leads to produce output signals which are applied to the eight outputs. The bus network comprises a local, a turning and an express bus for each row and column of the array and repeater means for partitioning said buses of a given row or column so as to form bus segments. The bus network provides for transfer of data to the cells of the array without using the cells as individual wires.

Bus interface logic for computer system having dual bus architecture

Abstract: A computer system is provided, comprising system memory and a memory controller for controlling access to system memory, a central processing unit electrically connected with the memory controller, and a bus interface unit electrically connected to the memory controller by a system bus and electrically connected to an input/output device by an input/output bus. The bus interface unit includes translation logic for temporarily storing, in response to a predetermined set of operating conditions, data transferred between the system bus and the input/output bus through the bus interface unit. The predetermined set of operating conditions occur when (i) the memory controller on behalf of the central processing unit writes data to the input/output device, or (ii) the memory controller on behalf of the central processing unit initiates a read or write cycle destined for the input/output device acting as a slave on the input/output bus, and the data bus width of the memory controller is greater than a corresponding data bus width of the input/output device.

Automatic signal termination system for a computer bus

Abstract: An automatic termination system for an end terminated bus especially useful with the SCSI bus. When utilized with a computer device, for example, a storage subsystem, configuration or reconfiguration of the bus can be automatically effectuated without concerns for inappropriate signal termination of the bus. The invention comprises a circuit which determines if any additional devices have been coupled to the bus and enables an active terminator chip if none is detected. Should another device be coupled onto the bus, the active terminator chip is automatically disabled.

Method and apparatus for communicating data across a bus bridge upon request

Abstract: A method of a processor communicating data across a bus bridge to a processing apparatus on a bus including the steps of storing the data into a processor memory, notifying the bus bridge, coupled to the processor and a bus, that the data is in the processor memory, reading the data from the processor memory upon request of the bus bridge, and forwarding the data from the bus bridge to the processing apparatus across the bus. In addition, an apparatus for a processor to communicate data across a bus bridge to a processing means on a bus including an apparatus for storing the data into a processor memory, an apparatus for notifying the bus bridge, coupled to the processor and a bus, that the data is in the processor memory, an apparatus for reading the data from the processor memory upon request of the bus bridge, and an apparatus for forwarding the data from the bus bridge to the processing apparatus across the bus.

Data transfer method and apparatus for communication between a peripheral and a master

Abstract: Data transfer apparatus (211,213) for a radiotelephone peripheral using a time multiplexed data bus for communication with a bus master of the radiotelephone couples peripheral devices external to the radiotelephone and other user information inputting devices, such as a handset for a cellular mobile radiotelephone, to the radiotelephone's central processor and speech processor. The data transfer apparatus generates time slots in frame formats in which the information is sent over the data bus. The entire message, information bits and the header, sent in a time slot from a peripheral device to the bus master is used to determine bus contention. Bus contention resolution during the start-up of data bus operation sets the priority with respect to other data transfer apparati with which a peripheral device's data transfer apparatus is able to access the bus during normal operation.

Serially controlled programmable test network

Abstract: A connector and data analyzer operate with a network of data storage devices connected to a serial data link. An arbitrarily large number of data storage devices may be connected via a serial data link with use of the connectors. Each device is connected to the serial data link by a connector. In one aspect of this invention, the converter is a microprocessor based system which functions to interface with the serial data link network and the bus attached to the peripheral device. In one embodiment, the microprocessor based system is generally composed of a network processor system and a device processor system. The converter may comprise a network processor which functions to maintain network continuity, monitors the serial data link for commands to the selected peripheral device, and provides command and information to a programmable device processor portion of the converter. The programmable device processor is configurable to interface with various bus requirements, and transfers control and data information to and from the peripheral device over the device bus. An important application of this invention is in providing a network for testing or analyzing peripheral devices via a host computer.

Method and apparatus for controlling dual bus system

Abstract: A method and apparatus for controlling a dual bus system, capable of realizing high speed and continuous operation even if one of the buses of the dual bus system fails. The method and apparatus has a dual bus system, a plurality of electronic circuits connected to both buses of the dual bus system, and bus controller for providing a bus use allowance signal to one of the plurality of electronic circuits, the one electronic circuit being selected in accordance with bus occupation request signals issued from the plurality of electronic circuits requesting data transfer. If the bus occupation request signals for both buses of the dual bus system originates from the one selected electronic circuit and the outputs of the arbiters coincide, the bus use allowance signal is provided to the one selected electronic circuit for the allowance of occupying both buses of the dual bus system. A completion of data transfer at the dual bus system is determined when data transfer is completed at both buses. Continuous operation can be ensured immediately upon occurrence of a failure, and high speed operation of a computer system is possible.

Programmably configurable host adapter integrated circuit including a RISC processor

Abstract: The host adapter integrated circuit is a one chip high performance bus master host adapter for (i) connecting a first bus having a specified protocol for transferring information over the first bus and a first data transfer speed to a second bus having a specified protocol for transferring information over the second bus and a second data transfer speed, and (ii) transferring information between the two buses. The host adapter integrated circuit, hereinafter host adapter, includes a novel reduced instruction set computing (RISC) processor, a first interface module circuit connectable to the first bus and coupled to the RISC processor, a second interface module circuit connectable to the second bus and coupled to the RISC processor, and a memory circuit means connected to the first interface module circuit and to the second interface module circuit and coupled to the RISC processor. An I/O bus interconnects the first interface module circuit, the second interface module circuit, the memory circuit means, and the RISC processor. The I/O bus supports a read and a write operation by the RISC processor in single clock cycle of the RISC processor. The host adapter supports many features found in traditional add-in card SCSI host adapters. These features include bus master transfers, fast/wide SCSI, one interrupt per command, scatter/gather, overlapped seeks, tagged queuing, etc.

Arbitration control logic for computer system having dual bus architecture

Abstract: A computer system is provided comprising system memory and a memory controller for controlling access to system memory, a central processing unit electrically connected with the memory controller, and a bus interface unit electrically connected to the memory controller by a system bus and electrically connected to a plurality of input/output devices by an input/output bus. The bus interface unit is able to sense when said one of said input/output devices has completed a read or write operation over said input/output bus, and includes a buffer circuit wherein read and write data transferred between the system bus and the input/output bus via the bus interface unit is temporarily stored during the transfer. Arbitration control logic resides in said bus interface unit and interacts with a central arbitration controller which resides on the system bus. The central arbitration controller responds to the arbitration control logic to simultaneously perform (i) arbitration cycles wherein the central arbitration controller arbitrates between the plurality of input/output devices and the central processing unit to determine which of the input/output devices or the central processing unit should be granted control of the input/output bus and (ii) grant cycles wherein the central arbitration controller grants control of the input/output bus and extends control of the system bus to one of the input/output devices or the central processing unit.

Dynamic bus arbitration with concurrent same bus granting every cycle

Abstract: Apparatus and method for optimizing bus arbitration during direct memory access (DMA) data transfers across a nondedicated bus between a memory and/or a plurality of external devices each master having an arbitration priority. At least two nonoverlapping clocks are provided per transfer cycle and there is at least one transfer cycle per arbitration cycle. Arbitration priority requests are transmitted from each external device to an arbitration bus only at the rise of the first clock. At the end of the last clock, the priority code of the external device having the highest priority is determined to designate the external device which is to become bus master. Addresses and data are transferred between the designated bus master and the memory or another of the external devices via the nondedicated bus during the next cycle after a then active bus master relinquishes control. The priorities of the external devices can be changed dynamically. Arbitration cycles are pipelined in such manner that there is no loss of address or data transfer cycles. The then active bus master may extend the number of cycles during which it communicates with one or more external devices. A device designated as next in line as bus master may be preempted under a certain condition.

High speed bus transceiver with fault tolerant design for hot pluggable applications

Abstract: A high-speed data transport system for use in computers, switches, microprocessors or the like includes a low impedance differential bus and a plurality of transceivers connected to the bus. Each of the transceivers is provided with a driver circuit which places data onto the bus and a receiver for accepting data from the bus. The driver includes a pseudo-differential current driving circuit arrangement which sinks current from only one side of the bus while the other side of the differential bus is undisturbed. The receiver includes a differential comparator biased to a preferred output voltage level.

Data processing apparatus having first bus with bus arbitration independent of CPU, second bus for CPU, and gate between first and second buses

Abstract: An image processing apparatus containing a first bus, a second bus, a CPU connected to the first bus, a plurality of bus user units respectively connected to the second bus, a bus control unit connected with each of the plurality of bus user units and the CPU, and a bus connect/isolate gate unit connected with the first and second buses and the bus control unit. Each of the plurality of bus user units and the CPU contains a bus request signal sending unit for sending a bus request signal to the bus control unit when each of the plurality of bus user units and the CPU has a demand to use the second bus. The bus connect/isolate gate unit can isolate the first bus from the second bus, or connect the first bus with the second bus, under control of the bus control unit. The bus control unit receives the bus request signal from each of the plurality of bus user units and the CPU, determines one of the plurality of bus user units and the CPU, which sends the bus request signal to the bus control unit, as an acknowledged unit, sends an acknowledge signal to the acknowledged unit, makes the bus connect/isolate gate connect the first bus with the second bus when the CPU is the acknowledged unit, and makes the bus connect/isolate gate isolate the first bus from the second bus when the CPU is not the acknowledged unit.

Computer system in which a bus controller varies data transfer rate over a bus based on a value of a subset of address bits and on a stored value

Abstract: A computer system includes a bus and a plurality of devices coupled to the bus. A CPU within the bus controller generates addresses for data transfers to and from the devices. A bus controller generates control signals for the data transfers. A data transfer rate controlled by the control signals is varied so that the data transfer rate is optimal for data transfers to and from each device. The data transfer rate for a data transfer to or from a first device is based on a subset of address bits used by the CPU to address the first device.

Input/output (I/O) bidirectional buffer for interfacing I/O ports of a field programmable interconnection device with array ports of a cross-point switch

Abstract: A bi-directional buffer includes first and second unidirectional buffers connected for retransmitting signals in opposite directions between first and second buses. When an external bus driver pulls the first bus low, the first unidirectional buffer pulls the second bus low and generates a signal inhibiting the second unidirectional buffer from actively driving the first bus. When the external bus driver allows the first bus to return to the high logic level, the first unidirectional buffer temporarily supplies a high charging current to the second bus to quickly pull it up. Similarly, when an external bus driver pulls the second bus low, the second unidirectional buffer pulls the first bus low and generates a signal inhibiting the first unidirectional buffer from actively driving the second bus. When the external bus driver allows the second bus to return to the high logic level, the second buffer temporarily supplies a high charging current to the first bus to quickly pull it up. The bi-directional buffer includes a register for storing and reading out data representing successive logic states of a signal on the first bus, thereby providing a history of data appearing on the bus.

Fasolt: a program for feedback-driven data-path optimization

Abstract: The author describes Fasolt, a system that automatically optimizes the bus topology of a register-level data-path design. The unique aspect of Fasolt is that it uses information taken from a detailed layout model to choose optimizing transformations of the bus topology and the schedule of operations and transfers of an existing design. Such a system is called a feedback-drive system because it uses information derived at a low level (in this case, that of physical layout) to drive the selection of optimizing transformations at a higher level or levels (in this case, the scheduling and allocation levels). This allows the scheduling and topology synthesis steps to take wiring considerations into account in a way that has hitherto not been demonstrated in an automatic synthesis system. Experiments have shown that improvements in area, cycle time, and overall average delay can often be achieved in the same design using this approach. >

Distributed arbitration with programmable priorities

Abstract: A computer bus for transferring data among a plurality of modules coupled thereto, and having flexible, distributed bus arbitration. A plurality of data lines is operable to transfer bits of data among modules attached to the bus. A single arbitration line is coupled to each module, and is used to indicate whether the bus is available for the next bus cycle. A bus packet clock, called a BUP clock, is used to divide the bus into cycle periods called BUP time slots. An access time clock further divides these BUP time slots into time access slots. The BUP time slot is the unit of time for which a module will be granted access to the bus. The BUP time slot is selected so that modules will be granted access to the bus for a length of time defined by a packet length. Each module on the bus is provided with arbitration circuitry for determining whether that module will be granted access to the bus for the next BUP time slot. The arbitration circuitry counts the number of accessed time slots and compares the counter value to a module priority value and outputs a comparison time pulse when the values compare. A module with a lower priority number will pull the arbitration line low and claim the bus for the next BUP time slot if this module is requesting the bus for the next BUP time slot. Once a module has pulled the arbitration line low, no other module will be granted access to the bus for the next BUP time slot. When the next BUP time slot occurs, the module granted access to the bus for that period will be given access, and the counters of each module will be reset, and the priority of each module updated.