Showing papers on "Bus network published in 1996"

Architecture for an expandable transaction-based switching bus

Abstract: A switching bus architecture enables efficient transfer of data within a network switch having a plurality of ports interconnected by a high-performance switching bus. The architecture is preferably implemented as novel port interface and forwarding engine circuitry that cooperate to efficiently transmit data to, and receive data from, the switching bus in accordance with a 2-tier arbitration policy that ensures adequate port access to the bus. As a result of such a cooperating arrangement, the architecture improves the transfer efficiency of the switch by providing all ports sufficient bus access to convey accurate data throughout the switch.

Method and apparatus for directing data packets in a local area network device having a plurality of ports interconnected by a high-speed communication bus

Abstract: A one-chip local area network (LAN) device comprises more than one local area network interface ports each including one receiver (11-14), one transmitter (15-18) and one triplet processor (25-28), a high-speed data bus (24) to which individual ones of the plurality of local area network interface ports are connected, and a switch engine (34) connected to the high-speed data bus (24) and including a packet buffer controller (40), a high-speed data bus controller (42) and content-addressable memory manager (44). Each triplet processor (25-28), provides for the reading of a destination address in packets received from a corresponding one of the local area network interface ports and simultaneously provides for the cut-through transmission of packets received from other ones of the local area network interface ports that transfer the packets over the high-speed data bus (24).

Computer diagnostic board that provides system monitoring and permits remote terminal access

Abstract: A system management module (SMM) for a host server system includes a system management processor (SMP) connected to a system management local bus. The system management local bus connects to the system PCI bus through a system management central (SMC). The SMC includes the main arbitration unit for the PCI bus and also includes the arbiter for the system management local bus. The SMM includes a video controller and/or keyboard and mouse controller connected to the system management local bus to support remote consoling of the SMM. The video controller is further used for transmitting screen images to a remote computer system to facilitate system failure analysis. A plurality of system management remote units are provided for coupling to various components and busses within the host computer system. The system management remote units (SMR's) connect to the SMM via serial bus and permit the SMM to automatically monitor activities and operating conditions, including determining the source of interrupts on busses and detecting error conditions.

Method and apparatus for providing reset transparency on a reconfigurable bus

Abstract: A computer system includes a plurality of nodes, each having an associated unique identification and bus address, interconnected by point-to-point links. Device data records are maintained in a memory of the computer system wherein node unique identifications, which are bus reset invariant, are associated with corresponding node bus addresses, which are subject to change with bus resets. A driver associated with a source node initiates a bus transaction and specifies a reference identification for the destination node. The reference identification of the destination node is used to access the device data records to obtain the corresponding destination node bus address. When a bus transaction cannot be completed because a bus reset occurs, the device data records are updated to associate the new bus addresses of the nodes with the corresponding node unique identifications. The new destination node bus address is used to complete the bus transaction that was interrupted by the bus reset.

Hierarchical dual bus architecture for use in an electronic switching system employing a distributed control architecture

Abstract: A bus architecture for use in a data communication system provides a communication path between processors and one or more external devices including (M+1) hierarchical processors. Each of the processors is categorized into one of N hierarchies with M and N being a positive integer larger than 1, respectively, and N is smaller than (M+1). The bus architecture includes a bus having N buses, each of the buses coupled to one or more processors of a hierarchy and (N-1) linking means, and each of the linking means for coupling a bus of a hierarchy to a bus of a next hierarchy.

Address space architecture for multiple bus computer systems

Abstract: An information processing system comprises a processor, a first bus for conducting signals in accordance with a first bus protocol that does not support I/O address signals; a second bus for conducting signals in accordance with a second bus protocol that supports input/output (I/O) address signals; and a bridge circuit for coupling the first bus to the second bus. The processor includes a circuit for emitting address signals and an address type signal directed to a selected peripheral device. The bridge circuit comprises a filter for determining whether the address signal emitted by the processor corresponds to a peripheral device coupled to a bus subordinate to the bridge circuit; and a translation circuit, coupled to the filter, for translating signals in accordance with the first bus protocol to signals in accordance with the second bus protocol for transmission to the selected peripheral device.

Secondary I/O bus with expanded slot capacity and hot plugging capability

Abstract: A computer system is provided which supports an increase in the number of pluggable cards on the secondary I/O bus by using driver/receiver modules and direction control logic in place of more complex and more expensive bus to bus bridges. The number of pluggable cards on the I/O bus in a computer system is limited by the electrical loading of each card and the frequency of operations on the bus. Reducing the bus frequency provides more signal propagation time. The added signal propagation time supports the extension of the bus by driver/receiver modules and logic which controls the direction the driver/receiver modules drive the bus signals. Further, the driver/receiver modules support changing the hardware configuration of the system by adding or removing an I/O card without the need to cease data processing activity for the entire computer.

Hierarchical bus structure access system

Abstract: A system and method for reducing the time required to access peripheral devices or to perform peripheral device operations in a multiple bus architecture or hierarchical bus structure environment. A memory device is used to remember which addresses generated responses on which busses. The memory device is accessed in subsequent operations to eliminate the procedure for determining which bus is attached to the desired peripheral.

Method for fault-tolerant communication under strictly real-time conditions

Abstract: A method for fault-tolerant communication under strictly real-time conditions in a local network uses a double bus architecture for reporting faults and for tolerating global bus faults. An active fault detection and notification mechanism is provided in order to safeguard consistency in the case of a fault and in order to comply with time limits regarding transmission of data. During fault-free operation, all of the process data are transmitted in one of the redundant bus systems and status information is transmitted in the other bus system. In the case of a fault, each bus is used as a watchdog bus in order to notify the network subscribers of faults occurring in the respective other bus system. The method can be used in process-oriented control and automation systems which have stringent requirements regarding reliability and real-time behavior.

Atm bus system

Abstract: An ATM bus 11 is a bus for performing data transfers in an asynchronous transfer mode, while a control bus 8 is a bus for transferring control signals sent out by a central control section 1 in order to control bus users 10a ~ 10d. The bus users 10a ~ 10d and a bus arbitration circuit 12 are connected to this ATM bus. The bus users 10A ~ 10d are ATM bus users. When the bus users 10a ~ 10d simultaneously issue bus use requests, the bus arbitration circuit 12 selects a single bus use request from among these requests. Then, all of the bus users are sent data identifying the bus user which issued the selected bus use request. As a result, only the selected bus user begins a data transfer operation using the ATM bus 11.

Physical-to-logical bus mapping scheme for computer systems having multiple PCI bus configuration

Abstract: A Plug-and-Play (PnP) configuration driver initilization routine and PnP configuration utility for use in PCI bus architectures supporting dynamic I/O bus configurations. The PnP configuration driver includes a logical-to-physical PCI bus mapping scheme maintaining a PCI bus mapping table, and creating a logical-to-physical map table at start-of-day. PCI device drivers access devices through the logical bus numbers, thereby avoiding errors resulting when physical bus numbers change as a result of the addition or removal of buses within a computer system supporting dynamic I/O bus configurations.

Bus-to-bus bridge in computer system, with fast burst memory range

Abstract: A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-(E) ISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. The system bus is superpipelined, in that transactions overlap. A fast burst transactions are allowed between the bridge and main memory, i.e., requests which can be satisfied without deferring or retrying are applied to the system bus without waiting to get a response from the target. A range of addresses (e.g., system memory addresses) is defined to be a fast burst range, and any address in this range is treated differently compared to addresses outside the range. The bridge is programmed, by configuration cycles, to establish this fast burst range, within which it is known that an out-of-order response will not be received. When a transaction reaches a bridge interface from the PCI bus, and it is recognized that the address is within the fast burst range, then the fast burst mode is allowed, and write or read requests can be issued without waiting for the snoop phase, since there is no possibility of defer or retry.

Switch network extension of bus architecture

Abstract: An electronic switching and data transmission system for interconnecting a plurality of buses. A switching network interconnects several multi-drop buses using adapters to connect the buses to the switching network. The adapters implements hardware functions to appear to software as if all devices on the several buses were attached to a single large bus. The system permits higher speed transfer modes by eliminating multi-drop bus limitations.

Network switch including a switch manager for periodically polling the network ports to determine their status and controlling the flow of data between ports

Abstract: A network switch including one or more network ports for receiving and transmitting data is disclosed. The network switch also includes a processor, a switch manager, and memory. Each port includes a network interface, a data bus interface, and a processor port interface. A data bus is coupled to the data bus interface of each of the ports and the switch manager. A processor bus is coupled to a processor, the switch manager, and to the processor port interface of each of the ports. A memory bus is coupled to the memory and the switch manager. The switch manager periodically polls each of the network ports to determine the status of each port. The switch manager controls the flow of data between the network ports and memory based on the port status. The separate processor bus allows the processor to perform overhead functions, such as monitoring, determining status and configuration, without consuming valuable data bus bandwidth.

Video peripheral circuitry exercising bus master control over a bus of a host computer

Abstract: A video peripheral board for providing video I/O capabilities to a general purpose host computer. The video peripheral board comprises a video I/O port configured to connect a video device, a bus interface circuit, and control logic. The bus interface circuit is configured to connect the video peripheral board into a system bus of the host computer, and is capable of becoming bus master of the system bus. The control logic is configured to control the bus interface circuit to effect transfer of video data between the video I/O port and storage of the host computer, the video data passing through the video I/O port in real time.

Computer system with PCI repeater between primary bus and second bus

Abstract: A PCI repeater coupled between a primary bus and a secondary bus transparently decodes upstream transactions by halting operations on the secondary bus while the transaction is decoded on the primary bus. A clock disable signal is internally generated to temporarily disable the bus clock on the secondary bus. Transactions initiated on the secondary bus are first sent upstream regardless of whether or not the target is upstream. If the transaction is not positively claimed by a target on the upstream bus, the PCI repeater subtractively claims the transaction. Special upstream decoding logic in the PCI repeater is avoided by sending the transaction upstream and using the inherent decoding logic of PCI devices.

HDLC integrated circuit using internal arbitration to prioritize access to a shared internal bus amongst a plurality of devices

Abstract: This invention relates to an integrated HDLC circuit of the type including at least one HDLC controller and one DMA controller, and means for organizing the access to a first external bus for connection to an external memory, via an internal bus to which are connected different entities, which require to have access to the external memory, the internal bus being connected to the first external bus via a memory controller integrated in the HDLC circuit.

Method and apparatus for controlling bus arbitration in a data processing system

Abstract: A method of controlling bus arbitration using an arbitration bit to lock ownership of the bus and prevent bus grants pending completion of a predetermined sequence. In a data processing system (15) having multiple potential bus masters, competing bus ownership requests are resolved by an arbiter (9) resident on one of the bus masters (11). In one embodiment, for execution of a sequence of inseparable cycle data accesses, a central processing unit (3) causes an arbitration bit (22) in a control register (20) to be set. Once the arbitration bit (22) is set, the arbiter will effectively lock the bus, and will not provide a bus grant signal until the arbitration bit (22) is cleared. A timer (7) counts to a predetermined value, where upon completion the arbitration bit is cleared allowing arbiter (9) to provide bus grant signals. The present invention allows locking of bus arbitration during a pending inseparable sequence of data accesses without the use of special instructions or external signals.

Method and system for apportioning computer bus bandwidth

Abstract: A method interfaces a plurality of bus requesters with a computer bus. The method apportions the bus bandwidth among the bus requesters by assigning to each bus requester a bus bandwidth portion that is based on the bandwidth of the bus requester. The method identifies a requester bandwidth for each of the bus requesters and sums the requester bandwidths to obtain a total bandwidth. The method determines, for each of the bus requesters, a weighting value representing the ratio of the bus requester bandwidth to the total bandwidth. The method apportions the bus bandwidth among the bus requesters by assigning each bus requester a bus bandwidth portion that reflects the weighting value of the bus requester. Apportioning the bus bandwidth based on the weighting values causes the requester bandwidth of each bus requester to be reduced by the same percentage when the bus saturates.

Master-target based arbitration priority

Abstract: A system management module (SMM) for a host server system includes a system management processor (SMP) connected to a system management local bus. The system management local bus connects to the system PCI bus through a system management central (SMC). The SMC includes the main arbitration unit for the PCI bus and also includes the arbiter for the system management local bus. The SMM includes a video controller and/or keyboard and mouse controller connected to the system management local bus to support remote consoling of the SMM. The SMC includes logic to monitor PCI cycles and to issue error signals in the event of a system error. The SMC also isolates failed components by masking request, grant and interrupt lines for the failed device. Further, if a spare component is provided, the SMC permits dynamic switching to the spare. In addition to detecting errors and performing survival and maintenance operations, the SMC enhances system performance during normal operations by supporting master-target priority determinations to more efficiently arbitrate mastership of system busses such as the PCI bus.

Telephony-enabled network processing device with separate TDM bus and host system backplane bus

Abstract: A PC-based server platform includes a first backplane bus used for transferring data and commands to various PC peripheral devices. A network router and a telephony endpoint card are coupled to the backplane bus and separately coupled through a second Time Division Multiplexed (TDM) bus. The router includes interfaces to various packet switched networks such as a Wide Area Network (WAN) and a Local Area Network (LAN). The TDM bus is used to route telephony data between the different Internet Protocol (IP)-based networks and the telephony card independently of the host system. The PC host processor also uses the router as a standard LAN interface for transferring data packets. A DSP voice processing card is coupled between the backplane bus and the TDM bus to compress and decompress the telephony data transferred on the TDM bus.

Expandable communication cell bus for multiplexing and concentrating communication cell traffic onto high speed lines

Abstract: A communication interface with an expandable multilane cell bus that enables conversion of communication traffic received over a set of low speed or narrow band communication links according to a first communication protocol into a series of communication cells according to a second communication protocol. The cell bus enables concentration of the communication cells for transfer over a high speed communication link according to the second protocol. The communication interface includes a cell bus master that polls slave service modules while transferring communication cells to the service modules over a unidirection transmit portion of the cell bus and while receiving communication cells over a unidirection receive portion of the cell bus.

Bus-based communication synthesis on system-level

Abstract: We present an approach to automatic generation of communication topologies on system-level. Given a set of processes communicating via abstract send and receive functions and detailed information about the communication requirements of each process, we first perform a clustering of data transfers. This results in groups of transfers suited to share a common bus. For each of these clusters we execute a bus generation algorithm which schedules bus accesses in order to minimize the total communication costs. Other than previous approaches, we infer RAM, if necessary, and consider data-dependencies as well as periodic execution of processes, like in VHDL. An example demonstrates the efficiency of the developed algorithm.

ATM switch with integrated system bus

Abstract: A network switch includes a plurality of cell processing units coupled together via a switch bus. In a preferred embodiment, the switch bus supports the peripheral component interconnect (PCI) bus protocol. Each cell processing unit includes a segmentation and reassembly unit (SAR), a RISC processor, a port processor, and a bus control unit. The SAR generates cells from frames of data stored in memory and transfers those cells to a destination mailbox in response to commands from from the RISC processor. The SAR assembles a cell within an internal register by combining cell header information with payload data read from memory. Once a cell has been assembled, it is sent to the bus controller for transmission across the switch bus to an address given by a mailbox number. Cells are transferred across the switch bus using a PCI burst write to the mailbox. A reassembly function gathers 48-byte cells into one or more larger output buffers. Cell reassembly is triggered by another RISC processor command. During reassembly, cell header information is discarded and the data payload bytes are read to an internal buffer within the SAR. The payload data is then written to a memory location pointed to by a buffer memory pointer. The switch bus 14 is also used for the transfer of control information between configuration registers of the cell processing units 12.

Shared bus system with transaction and destination ID

Abstract: To reduce latency on a shared bus during bus arbitration, a novel shared bus system uses device select lines between a bus arbiter and the bus devices to select the bus slave concurrently with the granting of the shared bus to the bus master. Specifically, a bus device requests the use of the shared bus by driving an active state on a bus request terminal and driving a destination ID value corresponding to the desired bus slave to the bus arbiter. The bus arbiter then drives an active state on a bus grant output terminal coupled to the bus grant input terminal of the requesting device. Concurrently, the bus arbiter drives an active state on the device select output terminal coupled to the device select input terminal of the desired bus slave. In addition posted read request tagging can be simplified using a transaction ID bus to supplement the shared bus.

Optical communication network

Abstract: In an optical communication network in which a plural number of nodes are connected to each bidirectional broadcasting bus, and a node communicates with another using the packets, or an optical communication network in which a plural number of nodes are connected to a bidirectional broadcasting bus, and a node communicates with another using the packets, each node comprises carrier sensing means for sensing a carrier on the broadcasting bus, and jamming detecting means for detecting a jamming state of received signals.

Stop clock throttling in a computer processor through disabling bus masters

Abstract: Microprocessors are often used in portable equipment that run on battery power. Thus, microprocessors used in such environments should save power when ever possible. Processors that have internal cache memories and allow external bus masters present a difficult case. Such processor's cannot enter a low power state since an external bus master may attempt to access a memory location that is represented in the internal cache. The present invention introduces a method and apparatus for allowing a processor having an internal cache to enter a low power state even though there may be other bus masters. A bus idle timer or an operating system monitors the bus to determine if the system bus is idle. When the system bus is idle, a bus arbiter is disabled to prevent bus activity. The processor then enters the low power state. When there is an interrupt caused by an external bus master, the processor is awaked from the low power state and the bus arbiter is re-enabled such that future bus transactions can occur.

Buffer reservation method for a bus bridge system

Abstract: A method for transferring data through a bus bridge. The bus bridge includes a number of data buffers for storing data, prefetching data and write posting data. A device communicating with the bus bridge may reserve a buffer by one of two reservation mechanism. The reservation mechanism provides the bus bridge with the address and byte count. The reservation may also be forwarded to any upstream bus bridges. The reserved buffers are prefetched for efficient use of bus access. Data is prefetched and flushed according to alternative algorithms if a buffer is not reserved.

Subscriber input/output device of high-speed packet switching system with parallel common bus type

Abstract: A subscriber input/output device of a high-speed packet switching system with a parallel common bus type is disclosed. The subscriber input/output device uses a coaxial cable to establish a star network of a radius of hundreds of meters, and the star network is arbitrated by a polling method to be used as a near communication network or an internal link network of a large scale communication system. The high-speed performance of 320 Mbps-class with a relatively simple medium access protocol for transmitting data through a common parallel bus is obtained, and broadcasting and multicasting are supported.

Asynchronous transfer mode (ATM) segmentation and reassembly unit virtual address translation unit architecture

Abstract: An apparatus and method for translating a virtual address to a physical address utilizing an address translation unit implemented within a network interface card is described. The address translation unit of the present invention is utilized in a computer system. The computer system comprises a first bus; processors with embedded caches and memory coupled to the first bus; a second bus; a network logic coupled to the second bus, wherein the network logic includes an address translation unit; and a bus bridge coupled to the first bus and to the second bus.