Showing papers on "Bus network published in 1997"

Multi-tier architecture for control network

Abstract: A multi-tier, master-slave control network has at least three data buses. A first-tier master node and a plurality of first-tier slave nodes are connected to a main data bus. One or more first-tier slave nodes are connected to secondary data buses. The secondary data buses are connected to second-tier slave nodes, and the first-tier slave node connected to the secondary data bus acts as a master node with respect to the secondary data bus. One or more second-tier slave nodes may be connected to tertiary data buses to provide another layer of control nesting. The tertiary data buses are connected to third-tier slave nodes, and the second-tier slave node connected to the tertiary data bus acts as a master node with respect to the tertiary data bus. A preferred embodiment of the control network provides redundant backup control for a master node at each level of the hierarchy in which the slave nodes connected to a particular data bus are provided with means for detecting a failure of the master node and for taking over for the master node when such a failure occurs. The master node and slave nodes each have an uplink transceiver and a downlink transceiver, with the downlink transceiver ordinarily isolated by switches from the common bus. The switches may be closed to connect the node to the same data bus as the uplink transceiver, allowing the node to become a master node with respect to that particular data bus.

Reconfigurable network interface apparatus and method

Abstract: A reconfigurable computer network interface device (10) includes a reconfigurable controller (12), reconfigurable bus interface (22), and reconfigurable transceiver (14). The device (10) also includes a configuration control arrangement (20) and on-board memory (16) for storing configuration instructions. The preferred form of the invention also includes an arrangement for receiving configuration instructions from an external source. The reconfigurable bus interface (22) may be configured by hardware set-up and operational software instructions to emulate a bus interface for any of a number of different computer bus architectures. A bus adapter (26) connects between a bus port (39) associated with the reconfigurable bus interface (22) and the computer bus to provide the physical connection between the device (10) and the host computer. The reconfigurable transceiver (14) is reconfigurable by hardware set-up and operational software instructions to communicate in any one of a number of different network hardware protocols. A media connector (24a, 24b) cooperates with a transceiver port (23a, 23b) associated with the reconfigurable transceiver (14) to provide the physical connection between the device (10) and network medium (32a, 32b). The reconfigurable controller (12) is configurable by hardware set-up and operational software instructions to communicate in any of a number of different software protocols. Thus, the reconfigurable computer network interface device (10) may operate as a network card, bridge, router, brouter, or gateway between substantially any type of computer and any type of computer network.

Openbus system for control automation networks

Abstract: A novel control automation system for enabling I/O boards to access communication networks for receiving and transmitting real time control information over a communication network is disclosed. The system includes a control bus, a node controller and a development system. External hardware that connects to I/O devices such as sensors, motors, monitors, machines, etc. can be connected to the invention via I/O boards that receives and transmit digital signals, representing control information, to the bus. The bus functions as the hub of operation, receiving network communications, processing cooperative logic and transmitting information over the communication network. The bus enables single or multiple controllers to access real time information generated by the attached hardware. The bus also enables the execution of I/O operations that originated in external controllers and transmitted over the communication network. The bus allows any I/O control board having a common interface, such as ISA, PCI, Compact PCI, etc., to connect to the bus by attachment to one of its slots. An intelligent embedded implementation process provides the logic necessary to enable the connectivity between the I/O boards and the communication network. The development system includes a real-time compiler for generating p-code to be executed on the real-time kernel running in the node controller. The real-time compiler generates p-code from the combination of event triggers, event actions and program logic making up the user's application.

A network switch with a multiple bus structure and a bridge interface for transferring network data between different buses

Abstract: A network switch includes a plurality of first network ports coupled to a first bus, a plurality of second network ports coupled to a second bus, a bridge interface enabling data transfer between the buses, a switch manager controlling the flow of network data, and a processor for performing supervisory and control functions. The first and second network ports operate according to different network protocols, and the first and second buses operate according to different bus standards. During packet data transfers across the first bus, the bridge interface emulates a first network port. During packet data transfers across the second bus, the bridge interface primarily acts as a slave to the second network ports by storing control lists for execution by the second network ports, thus relieving the processor of performing overhead functions associated with data transfers across the second bus.

Deterministic serial bus communication system

Abstract: An apparatus and method for deterministically communicating data between multiple nodes in a fashion that is consistent with the Controller Area Network ("CAN") communications protocol. The system applies to multiple nodes that functional blocks within an operating system environment and to multiple nodes that are each connected to a serial bus. The system utilizes standard CAN error checking, bus arbitration and message formatting and therefore uses standard CAN controllers and transceivers. One node on the bus is selected as the master node. The master node issues a periodic synchronization signal which defines time divisions within which the operations of each node and communications over the CAN bus are organized. Data, particularly real-time data, is transmitted between nodes on the CAN bus during a known time division. Standard CAN bus arbitration is used to ensure that real-time data is transmitted over the CAN bus prior to the transmission of non-real-time data. This ensures that real-time data is, if appropriate, transmitted during each time division.

Bus structure for modularized chip with FPGA modules

Abstract: An on-chip bus structure for use in a modularized integrated circuit chip including an FPGA module(s). The bus is intended for memory mapped data transfers between circuit modules, for instance master, slave, master/slave, bus controller, and bus monitor type modules. Each circuit module is an on-chip function block including a bus interface and communicates by a predefined set of bus signals; at least one module is an FPGA (field programmable gate array). Each module acts as a bus master when it initiates data read or write operations, or may be addressed during a bus read/write operation and thereby acts as a bus slave. This bus and module structure allows implementation of a system on a single chip.

Single chip network adapter apparatus

Abstract: A single chip network adapter apparatus has each component disposed on a single semiconductor chip. The network adapter includes a host interface circuit which is adapted for connection directly to a host system bus. The host interface circuit sends information to and receives information form the host system bus, and has random access memory coupled thereto. A processor is coupled to the random access memory and formats information received from the host system bus to a network protocol format. The processor also converts information received in a network protocol format to a form suitable for the host system bus. A network interface circuit is coupled to the random access memory and is adapted for connection directly to a network. The network interface circuit sends information formatted by the processor to the network and receives information to be converted by the processor from the network.

Apparatus for and method of communicating among devices interconnected on a bus

Abstract: An information communication system has a plurality of nodes connected by both an information transmission bus and a signalling channel The information transmission bus is used to carry messages between devices attached to the nodes of the network The signing channel is used to signal nodes that a message transmission is about to occur Based on the devices connected to the nodes, the appropriate communication protocol can be set up and resources allocated on the information transmission bus to efficiently transfer information The invention allows a device acting as a message source to communicate with another device at a first node using a first protocol and to communicate with a different device at a second node using a second protocol The protocols can be stored in the devices attached to the nodes or a control node can be used

System, apparatus, and method for managing power in a computer system

Abstract: A computer system is provided for monitoring the activity of a bus controller of a processor and responsive thereto for controlling the power consumption of a target controller such as a memory controller coupled to the bus controller. The computer system includes a bus, a processor having a bus controller coupled to the bus, and a bus activity monitor, coupled to the bus controller, generating a bus activity signal indicative of activity in the bus controller. The computer system also includes a target controller, coupled to the bus controller, for controlling the exchange of information between the processor and a target circuit. The target controller has an input for receiving a sequencing signal. The computer system additionally includes a power management circuit for controlling a power consumption of the target controller. The power management circuit has an input for receiving the bus activity signal and, an output for generating the sequencing signal in response to the bus activity signal.

Field programmable gate array with distributed ram and increased cell utilization

Abstract: A field programmable gate array has a matrix of programmable logic cells (11; 12) and a bus network of local and express bus lines (19, 21, 23, 25). The bus network effectively partitions the matrix into blocks (15) of cells with each block having its own distinct set of local bus lines. Express bus lines extend across more than one block of cells by means of repeater switch units (27) that also connect local bus lines to express bus lines. The grouping of cells into blocks with repeaters aligned in rows and columns at the borders (13) between blocks creates spaces at the corners of blocks that can be filled with RAM blocks (83), other memory structures, specialized logic structures or other dedicated function elements that are connected to the bus network. The RAM blocks (83), other memory structures, specialized logic structures or other dedicated function elements that are connected to the bus network. The RAM blocks (Fig. 13) can be single or dual port SRAM (85) addressed through the bus lines (86, 178, 179).

Integrated circuit for coupling a microcontrolled control apparatus to a two-wire bus

Abstract: An integrated semiconductor circuit for an electronic control unit has a microcontroller with a bus protocol function for communicating with other microcontrolled control units via a Controller Area Network (CAN) by way of a two-wire bus. The invention includes a bus-fault-tolerant transceive function which permits communication even when a bus fault is present. A bus fault recognition and response device disconnects the bus from its normal connections and alters its termination characteristics when a fault is detected.

Bus system, printed circuit board, signal transmission line, series circuit and memory module

Abstract: There are provided plural synchronous RAMs, a memory controller, a bus for inputting the signal output from the memory controller 1a to the synchronous RAMs, and a bus for inputting the signals output from the synchronous RAMs to the memory controller. Each of the buses has a main line and two stub lines connected to the trunk like. Each of the synchronous RAMs is connected to the corresponding stub line so that the sum of the bus length of the bus between the synchronous RAM and the memory controller and the bus length of the bus between the synchronous RAM and the memory controller is substantially constant among all of said synchronous RAMs. Therefore, the signal transmission time between the bus master and the plural bus slaves can be shortened without increasing the number of pins of the bus master while keeping the signal transmission time substantially constant among the plural bus slaves.

Multi-mode, multi-channel communication bus

Abstract: A dynamically reconfigurable, multi-mode, multi-channel communication bus. The bus may be dynamically reconfigured into a plurality fo segments, or slices, to provide a relatively wide unified bus, or smaller versions of the bus. This allows multiple bus masters to coexist at the same time that control the bus. The protocol is adaptive in that bus widths dynamically change to allow addition or removal of bus masters at any time. Bus acquisition delays caused by bus arbitration latency using a packetized protocol regime are drastically reduced or eliminated in some systems by using the present bus. The bus demonstrates relatively high efficiency.

High speed multimedia data network

Abstract: A low cost, high speed multimedia data network is disclosed. The network preferably includes a fiber optic data bus arranged in a star topology configuration. Various types of devices or nodes may be placed in communication with the bus via a specially designed interface. The interface allows a device to communicate with the high speed network without requiring that the device have the processing power to receive and transmit data according to the protocols and demands of the network. The interface may be configured to match the complexity of its associated device. For intelligent devices, the interface may allow some of the network-related functions to be performed by the device itself. For non-intelligent (or "dumb") devices, the interface performs substantially all of the network-related functions. In general, the interface provides the capability of insulating a node from the complexities of the high speed network by receiving data from and providing data to the node according to the node's data format, and receiving data from and providing data to the network according to the network's data format. The general messaging protocols are designed to facilitate the transfer of data in a star topology configuration, while also facilitating the relatively low cost and flexible implementation of the network.

Management communication bus for networking devices

Abstract: A management communication bus for enabling management of network devices in a network system. The network system includes at least one bus master device and at least one slave device, where the bus master and slave devices are distributed within the network devices. Each network device includes a slave device or a bus master device or both. The bus includes several conductors for state signals for defining four states for arbitration, for slave identification, for asserting an address and for asserting data corresponding to the address. The bus further includes several conductors for data signals for transferring information data depending upon the different states, where the information data includes bus request, slave identification, the address and the data corresponding to the address. Each bus master includes an interface to the bus to step through each of the states for controlling each cycle. Each bus master and slave device includes an identification number with a predetermined priority.

Method for powering elements connected in a two-wire bus network transmitting both power supply and data information pulses

Abstract: The present invention relates to a powering method for elements connected in a two-wire bus type network wherein information frames of predetermined length are transmitted at predetermined times. The method consists of regularly sending on the two-wire bus a power supply pulse between the end of an information frame and the beginning of the next frame.

Three bus server architecture with a legacy PCI bus and mirrored I/O PCI buses

Abstract: A fault-tolerant computer system includes a processor and a memory, connected to a system bus. The system includes at least two mirrored circuits, at least two mirrored IO devices, a detection means and a re-route means. The two mirrored circuits each include an interface to the system bus, and an IO interface. The input/output interface of each of the mirrored circuits is connected to one of the two mirrored IO devices. Detection means detect a load imbalance in the data transfer between the system bus and either one of the two mirrored IO devices. In response to the detection of a load imbalance, the re-route means re-routes the data transfer between the system bus and the other one of the two mirrored IO devices. In another embodiment, a fault-tolerant computer system includes a first, second and third IO bus, legacy devices, and two IO devices. The first IO bus is connected to the system bus. The legacy devices are connected to the first IO bus. The second and third IO buses are each connected to the system bus. The IO devices are each connected to a corresponding one of the second and third IO buses. An other embodiment of the invention can be characterized as an apparatus for transferring data between at least one transport protocol stack and a plurality of network adapters coupled to a computer network that supports recovery from network adapter and a connection failure.

Backup control mechanism in a distributed control network

Abstract: A multi-tier, master-slave control network having redundant backup for a master node in which the slave nodes are provided with means for detecting a failure of the master node and for taking over for the master node in such circumstances. The master node and slave nodes are connected to a common bus. Each of the slave nodes has an uplink transceiver and a downlink transceiver, with the downlink transceiver ordinarily isolated by switches from the common bus. Each of the slave nodes has a timer programmed with a separate failure mode detection time period. When a slave mode fails to receive control messages from the master node for a period exceeding its programmed failure mode detection time period, the slave node takes over for the master node. Because each slave node has a separate failure mode detection time period, a priority is established in which the slave nodes will take over for the master node, and redundant master backup control is provided. A preferred embodiment of the control network has multiple buses, one bus for each tier, and each bus has a master node and a plurality of slave nodes, with each of the slave nodes capable of taking over for the master node on the slave node's particular bus.

Apparatus and method for entering low power mode in a computer system

Abstract: A power management circuit for managing low power modes in a computer system, which implements four power modes, from highest power consumption to lowest power consumption: RUN mode, SLEEP mode, IDLE mode, and STANDBY mode. The computer system includes a PCI bus and an ISA bus, with a CPU-PCI bridge to connect the host bus and the PCI bus and a PCI-ISA bridge to connect the PCI bus and the ISA bus. The power management circuit transitions from SLEEP mode to IDLE mode by first determining if the CPU-PCI bridge is parked on the PCI bus and if it is in SLEEP mode. The power management circuit then waits for one refresh period and for all internal queues to empty before checking again to determine if the CPU-PCI bridge is still parked on the PCI bus and if it is still in SLEEP mode. If true, the CPU-PCI bridge transitions to IDLE mode. The power management circuit also performs low power refresh cycles when it is in IDLE or STANDBY mode. In those modes, the memory controller in the CPU-PCI bridge is disabled to conserve power. The power management circuit performs the refresh cycles based off an external asynchronous clock. Further, the power management circuit drives certain PCI bus signals to a certain state to avoid leakage current due to the existence of a mixture of 3.3-volt and 5-volt components connected to the PCI bus.

Multiple parallel digital data stream channel controller architecture

Abstract: A multiple data stream channel controller (26) providing demand driven transport of multiple data streams concurrently in real time through a peripheral data channel (41) coupled between a general purpose processor system (12) and a special purpose processor system (36). The controller comprises a first bus master interface (24) coupled to a general purpose processor system bus (20), a second bus master interface coupled to a special purpose processor system bus (30), a segmentable buffer memory (not shown) and a controller (26) that directs the transfer of data segments between the first and second bus master interfaces via the segmentable buffer memory. The controller is responsive to signals provided by the special purpose processor bus (30) to request transfer of successive data segments from respective data streams staged in the segmentable buffer memory. The controller moderates the transfer of successive data segments of the respective data streams via the first bus master interface (24) to the segmentable buffer memory.

A computer system having a multimedia bus and comprising a centralized i/o processor which performs intelligent data transfers

Abstract: A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus or expansion bus, such as the PCI bus, and also includes a dedicated real-time bus or multimedia bus. Various multimedia devices are coupled to one or more of the expansion bus and/or the multimedia bus. The computer system includes a dedicated or centralized I/O processor coupled to one or more of the expansion bus and/or the multimedia bus which operates to direct or pull stream information through the system. The centralized I/O processor comprises a memory for storing data rate, data periodicity, data source, and data destination information for said multimedia devices. The computer system of the present invention thus provides much greater performance for real-time applications than prior systems.

Method of controlling the transfer of information across an interface between two buses

Abstract: A method and apparatus for interfacing buses includes a system interface processor coupled to a first bus and including a command register accessible via a second bus. A request buffer and a response buffer are provided which are accessible via the second bus and coupled to the interface processor. The request buffer can be used to store information to be transmitted from the second bus to the first via the interface processor while the response buffer can be used to store information to be transmitted from the first bus to the second bus via the interface processor. The interface processor may include a status register to indicate the status of the interface controller. The interface controller may also include a command register to receive commands transmitted over the second bus.

Computer system having a multimedia bus and including improved time slotting and bus allocation

Abstract: A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus or expansion bus, such as the PCI bus, and also includes a dedicated real-time bus or multimedia bus. Various multimedia devices are coupled to one or more of the expansion bus and/or the multimedia bus. The multimedia bus is preferably time sliced wherein time slices or time slots are allocated in proportion to the required bandwidth. Each multimedia device includes programmable time slotting logic which determines the appropriate time slot. In one embodiment, the time slices are each a constant size and a number of the equal sized time slots are allocated to respective data streams in proportion to the required bandwidth. Alternatively, the time slots are dynamically sized or allocated to data streams in proportion to the required bandwidth. The computer system of the present invention thus provides greater performance for real-time applications than prior systems.

Extended symmetrical multiprocessor architecture

Abstract: An architecture for an extended multiprocessor (XMP) computer system is provided. The XMP computer system includes multiple SMP nodes. Each SMP node includes an XMP interface and a repeater structure coupled to the XMP interface. The SMP nodes are connected to each other by unidirectional point-to-point links. The repeater structure in each SMP node includes an upper level bus, one or more transaction repeaters coupled to the upper level bus. Each transaction repeater broadcasts transactions to bus devices attached to a lower level bus, wherein each transaction repeater is coupled to a separate lower level bus. Transaction repeater includes a queue and a bypass path. Transaction originating in a particular SMP node are stored in the queue, whereas transactions originating in other SMP nodes bypass the incoming queue to the bus device. Multiple transactions may be simultaneously broadcast across the point-to-point link connections between the SMP nodes. However, transactions are broadcast to the SMP nodes in a defined, uniform order. A control signal is asserted by the XMP interface so that a transaction is received by bus devices in the originating node from the incoming queues at the same time and in the same order it is received by bus devices in non-originating nodes. Thus a hierarchical bus structure is provided that overcomes physical/electrical limitations of single bus architecture while maximizing bus bandwidth utilization.

Method and system for bus arbitration in a multiprocessor system utilizing simultaneous variable-width bus access

Abstract: A method and system for enhanced bus arbitration in a multiprocessor system having multiprocessors coupled to a system memory via a common wide bus. The common wide bus is subdivided into multiple sub-buses which may be accessed individually or in groups by a selected processor, or individual sub-buses may be accessed by multiple processors simultaneously. In response to one or more pending transactions, each processor outputs a request to bus arbitration logic for a number of sub-buses. A maximum number of sub-buses is specified for each processor and the processors are prioritized. Each time a bus request is received from a processor, the number of requested sub-buses is granted, if that number is equal to or less than the specified maximum number of sub-buses for that processor. If the requested number of sub-buses is greater than the specified maximum number of sub-buses for that processor the requested number is granted if no other processor has issued a bus request.

Redundant network management system for a stackable fast ethernet repeater

Abstract: Provided is a redundant network management system. Several network management modules (NMMs), preferably one for each repeater unit, are provided in a single repeater stack. The NMMs of the repeater stack communicate using a management bus. The modules communicate on the management bus by sending small messages, referred to as "frames." In a preferred embodiment, the present invention is preferably used in conjunction with a relatively simple and economical 8-bit management bus. This low cost implementation allows only one NMM to access the bus at any given time, and makes use of protocols by which multiple NMMs may use the management bus to communicate while ensuring that no two modules attempt to use the bus at the same time. Moreover, according to the present invention, only one NMM (referred to as the "master") will perform all of the network management functions for the stack at any one time. The remaining modules operate in "slave" mode. When in slave mode, the modules are on stand-by, ready to take the role of master if necessary. This master/slave relationship provides a level of fault tolerance and redundancy to the user in a seamless manner, thereby improving network performance and reliability.

Error generation circuit for testing a digital bus

Abstract: In order to test a parallel digital bus, an integrated circuit adapted for coupling to the bus has a bus error generation circuit which generates and/or simulates bus error conditions on the bus. During test, an error command is loaded into a command register of the bus error generation circuit via the bus. The bus error generation circuit then decodes the command, and either: 1) generates an error condition on the bus during a subsequent bus cycle, or 2) simulates an error condition on the bus during a subsequent bus cycle. A status configuration register in the integrated circuit and status configuration registers in other devices on the bus are then read to determine whether the integrated circuit and other devices properly detected and/or handled the generated or simulated error. By providing a bus error generation circuit in the integrated circuits coupled to a bus inside a personal computer, built-in test of the personal computer is facilitated.

Speech interface in a home network environment

Abstract: Home networks low-cost digital interfaces are introduced that integrate entertainment, communication and computing electronics into consumer multimedia. Normally, these are low-cost, easy to use systems, since they allow the user to remove or add any kind of network devices with the bus being active. To improve the user interface a speech unit (2) is proposed that enables all devices (11) connected to the bus system (31) to be controlled by a single speech recognition device. The properties of this device, e.g. the vocabulary can be dynamically and actively extended by the consumer devices (11) connected to the bus system (31). The proposed technology is independent from a specific bus standard, e.g. the IEEE 1394 standard, and is well-suited for all kinds of wired or wireless home networks.

System for multisized bus coupling in a packet-switched computer system

Abstract: A data transfer control system for a computer system having a packet-switched data bus, for controlling the transfer of data words from a device having one bus width to a device having a different bus width. The first bus may be the master bus, and the second bus is a bus of a functional unit, such as a memory or other device, connected to the computer system and coupled to the master bus. When the second bus is smaller than the first bus, the data transfer control system accommodates this by transferring only partial words per clock cycle to the second bus, effectively delaying the transference of data to a rate that the second bus can handle. The transfer rate factor is substantially equal to the ratio of the second bus width to the first bus width. In an alternative embodiment, the data transfer control system transfers the data words at substantially the full rate available, given the computer system's processor or clock speed and the width of the master bus, and the words are buffered before transference to the second bus. The speed of transference to the buffer is then not limited by the size of the second bus, but only by the size of the buffer, which preferably has an input bus at least as wide as that of the master bus. The system accommodates functional units of different sizes all to be couple to a master bus of a given size, where the different sizes may be larger or smaller than the master bus size, and accordingly the functional units can be built with optimal bus sizes for their particular functions without having to conform to a perhaps inappropriate, inefficient or expensive or wasteful master bus size.

Scaleable network system for remote access of a local network

Abstract: A network system that provides a scaleable and distributed architecture to enable a plurality of remote clients to access a local area network (LAN). The network system includes an access server that executes a network operating system (NOS), such as any standard NOS, to enable communication with the LAN, an access bus, an access device coupled to the access server and the access bus that cooperates with the NOS to establish a communication link between the access server and the clients, and at least one multiport device coupled to the access bus and coupled to one or more clients through corresponding wide area network (WAN) connections that cooperates with the access device to establish a communication link between clients and the access device. The access server is preferably implemented on an industry standard platform using industry standard components. The access bus is either a dedicated bus or a shared media bus, such as Ethernet. The multiport and access devices cooperate to link each client to the access server as though directly connected thereto. Each multiport device includes a plurality of port slots, each for receiving one of a plurality of communication cards coupled to a remote clients via corresponding WAN connections. Each communication card operates according to one of a plurality of different communication protocols.