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Showing papers on "Bus network published in 2002"


Patent
30 Sep 2002
TL;DR: In this paper, an interface device is connected to a host by an I/O bus and provides hardware and processing mechanisms for accelerating data transfers between a network and a storage unit, while controlling the data transfers by the host.
Abstract: An interface device is connected to a host by an I/O bus and provides hardware and processing mechanisms for accelerating data transfers between a network and a storage unit, while controlling the data transfers by the host. The interface device includes hardware circuitry for processing network packet headers, and can use a dedicated fast-path for data transfer between the network and the storage unit, the fast-path set up by the host. The host CPU and protocol stack avoids protocol processing for data transfer over the fast-path, freeing host bus bandwidth, and the data need not cross the I/O bus, freeing I/O bus bandwidth. The storage unit may include RAID or other multiple drive configurations and may be connected to the INIC by a parallel channel such as SCSI or by a serial channel such as Ethernet or Fibre Channel. The interface device contains a file cache that stores data transferred between the network and storage unit, with organization of data in the interface device file cache controlled by a file system on the host. Additional interface devices may be connected to the host via the I/O bus, with each additional interface device having a file cache controlled by the host file system, and providing additional network connections and/or being connected to additional storage units.

348 citations


Journal ArticleDOI
TL;DR: A new method to compute fitness function (ff) values in genetic algorithms for bus network optimization by means of a multicriteria analysis executed on the performance indicators obtained by the analysis of the assignment of the O/D demand associated to the considered networks.
Abstract: This paper focuses on a new method to compute fitness function (ff) values in genetic algorithms for bus network optimization. In the proposed methodology, a genetic algorithm is used to generate iteratively new populations (sets of bus networks). Each member of the population is evaluated by computing a number of performance indicators obtained by the analysis of the assignment of the O/D demand associated to the considered networks. Thus, ff values are computed by means of a multicriteria analysis executed on the performance indicators so found. The goal is to design a heuristic that allows to achieve the best bus network satisfying both the demand and the offer of transport.

199 citations


Patent
05 Apr 2002
TL;DR: An internal bus system for DFPs and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity, is presented in this article.
Abstract: An internal bus system for DFPs and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity. The bus system can transmit data between a plurality of function blocks, where multiple data packets can be on the bus at the same time. The bus system automatically recognizes the correct connection for various types of data or data transmitters and sets it up.

159 citations


Patent
24 Apr 2002
TL;DR: In this article, a network controller has a multiprotocol bus interface adapter coupled between a communication network and a computer bus, the adapter including a predictive time base generator; and a management bus controller adapted to monitor and manage preselected components coupled with one of the communication networks and the computer bus.
Abstract: A network controller having a multiprotocol bus interface adapter coupled between a communication network and a computer bus, the adapter including a predictive time base generator; and a management bus controller adapted to monitor and manage preselected components coupled with one of the communication network and the computer bus. The management bus controller is adapted to employ an Alert Standard Format (ASF) specification protocol, a System Management Bus (SMBus) specification protocol, an Intelligent Platform Management Interface (IPMI) specification protocol, a Simple Network Management Protocol (SNMP), or a combination thereof. The network controller also includes a 10/100/1000BASE-T IEEE Std. 802.3-compliant transceiver and media access controller coupled with the communication network; a buffer memory coupled with the MAC, wherein the buffer memory includes one of a packet buffer memory, a frame buffer memory, a queue memory, and a combination thereof; and a transmit CPU and a receive CPU coupled with the multiprotocol bus interface adapter and the management bus controller. The network controller can be a single-chip VLSI device in an 0.18 micron CMOS VLSI implementation.

87 citations


Patent
06 Jun 2002
TL;DR: In this article, a protocol selector unit is used to select a bus protocol I/O unit to communicate with the device over the universal bus, and the bus protocol unit communicates over the bus by using a protocol that is compatible with a device.
Abstract: A universal bus communicates information by one of plural bus protocols. A bus protocol selector is operable to select one of the plural bus protocols associated with a device interfaced with an information handling system and to communicate information over the bus with the selected bus protocol. An Input/Output chip includes a protocol selector unit that selects a bus protocol I/O unit to communicate with the device over the universal bus. The bus protocol I/O unit communicates over the universal bus by using a bus protocol that is compatible with the device. For instance, the one of plural available differential serial bus protocols is selected so that the bus protocol I/O unit communicates with the device using a bus protocol compatible with the device. In some instances, a bypass circuit configures the physical characteristics of the universal bus, such as by interfacing or removing a capacitor with the universal bus to support AC or DC coupled bus protocols.

74 citations


Journal ArticleDOI
TL;DR: In this paper, the authors formulated the transmission expansion problem (TEP) as an optimization problem and solved it using artificial intelligence tools such as the genetic algorithm, Tabu search and artificial neural networks (ANNs) with linear and quadratic programming models.

70 citations


Patent
05 Dec 2002
TL;DR: In this article, the authors propose an apparatus for connecting a computer bus to a network consisting of a network interface capable of coupling to an external network and an emulator coupled to the network interface.
Abstract: An apparatus for connecting a computer bus to a network comprises a network interface capable of coupling to an external network and an emulator coupled to the network interface. The emulator comprises a processor control block that can emulate a host processor coupled to the computer bus and a device control block that can emulate a device coupled to the computer bus.

67 citations


Patent
23 Oct 2002
TL;DR: In this article, a segmented CAN bus is proposed to isolate individual nodes of identical type when needed and the ability for a host to determine the network topology, which eliminates the need for jumpers, DIP switches, or other hardware requiring human intervention to uniquely identify the nodes on the network.
Abstract: A “segmented” CAN bus is provided that extends the cabling scheme of a CAN network to permit isolation of individual nodes of identical type when needed and the ability for a host to determine the network topology. In addition, the CAN bus cabling scheme automatically assigns unique addresses to nodes and guarantees that the network will always be properly terminated. This eliminates the need for jumpers, DIP switches, pre-installation programming, or other hardware requiring human intervention to uniquely identify the nodes on the network. Furthermore, because the physical node topology is determinable, equipment installation and anomaly diagnostics are facilitated.

64 citations


Patent
22 Oct 2002
TL;DR: In this paper, a node stores network topology information and programmed link establishment rules and criteria, and then determines whether it can form a communication link with a substitute node, in order to maintain connectivity with the network.
Abstract: Nodes in a network having a plurality of nodes establish communication links with other nodes using available transmission media, as the ability to establish such links becomes available and desirable. The nodes predict when existing communications links will fail, become overloaded or otherwise degrade network effectiveness and act to establish substitute or additional links before the node's ability to communicate with the other nodes on the network is adversely affected. A node stores network topology information and programmed link establishment rules and criteria. The node evaluates characteristics that predict existing links with other nodes becoming unavailable or degraded. The node then determines whether it can form a communication link with a substitute node, in order to maintain connectivity with the network. When changing its communication links, a node broadcasts that information to the network. Other nodes update their stored topology information and consider the updated topology when establishing new communications links for themselves.

56 citations


Patent
24 Sep 2002
TL;DR: In this paper, a serial bus is monitored in order to detect a quiescent period on the bus, and the bus signals to a first master device of the serial bus are interrupted to isolate the first bus master from the rest of the bus.
Abstract: A method and method of mastering a serial bus. A serial bus is monitored in order to detect a quiescent period on the bus. Responsive to a detection of a quiescent period, bus signals to a first master device of the serial bus are interrupted, isolating the first bus master from the rest of the bus. Once the first bus master is isolated, a second bus master may operate on the bus, free from potential deleterious interference from the first bus master. When the second bus master is finished operating, it may cause the re-coupling of the bus, restoring the capability of the first bus master to operate.

54 citations


Patent
Yann Stephan1
03 Apr 2002
TL;DR: In this article, the authors propose an approach to selectively access devices to the bus that communicates between one or more devices and a host machine by analyzing device characteristics and disabling the communication between the device and the host machine via the bus.
Abstract: Devices connected to a communications bus are selectively accessed to the bus that communicates between one or more devices and a host machine. On the basis of analyzed device characteristics, communication between the device and the host machine via the bus is enabled or disabled. Filtering software intercepts the results of a GET_DESCRIPTOR function and compares same with the contents of a disallowed device characteristic list. If the device is disallowed, data flow is remapped to a generic driver which halts configuration or communication on the bus. Alternatively, configuration/communication on the bus is halted for that device.

Patent
26 Apr 2002
TL;DR: In this paper, the authors present a system, methods, and bus controllers (12) for establishing communication with various network systems located on a network system, which is capable of recognizing that a new network device (16, 18, 20) has been added to an existing network and assigning it an address such that the added network device is identifiable on the network.
Abstract: The present invention provides systems, methods, and bus controllers (12) for establishing communication with various network systems located on a network system (10). Importantly, the systems, methods, and bus controllers (12) of the present invention are capable recognizing that a new network device (16, 18, 20) has been added to an existing network and assigning it an address such that the added network device is identifiable on the network. Further, the systems, methods, and bus controllers (12) of the present invention may update the operating schedule that outlines communication in the network system between the bus controller (12) and the network devices (16, 18, 20) to include commands for communicating with the added network device. The systems, methods, and bus controllers (12) of the present invention may also detect when a network device (16, 18, 20) has been disconnected from a network system (10) and remove the commands associated with the networked device from the command schedule.

Patent
Peter Fuhrmann1, Manfred Zinke1
06 Sep 2002
TL;DR: In this article, a communication network with at least two network nodes, with transmission channels for transmitting data packets between the network nodes and at least one active coupler, is considered.
Abstract: The invention relates to a communication network with at least two network nodes, with transmission channels for transmitting data packets between the network nodes, and with at least one active coupler The invention provides for coupler information to be attached to the data packets as they pass through the active coupler, and data-packet running-time information to be determined from the coupler information in a network node that receives a data packet

Patent
29 Jan 2002
TL;DR: In this article, a programmable data path accelerator is described, which operates on a file server that includes a network interface for communicating with one or more clients, including a network transaction queue.
Abstract: A programmable data path accelerator is described. The programmable data path accelerator operates on a file server that includes a network interface for communicating with one or more clients. The network interface includes a network transaction queue. A metafile processor is configured to communicate with the network interface across a first memory-mapped bus and is configured to communicate with the storage interface across a second memory-mapped bus. A data engine configured to communicate with the network interface across the first memory-mapped bus and to communicate with the storage interface across the second memory-mapped bus.

Patent
11 Jun 2002
TL;DR: In this paper, the number and weight of wires interconnecting a host and/or controller with a precision measurement assembly is reduced using a common or shared bus, which may be entirely electrical or may include optical fibers to reduce EMI susceptibility.
Abstract: The number and weight of wires interconnecting a host and/or controller (52) with a precision measurement assembly (40) is reduced using a common or shared bus. The bus may be entirely electrical or may include optical fibers to reduce EMI susceptibility. A custom bus or a known serial network bus such as CAN or SIRCOS may be used.

Patent
Peter A. Hawkins1, Colin Cook1
10 Jan 2002
TL;DR: In this article, a star Intelligent Platform Management Bus (IPMB) topology that uses independent intelligent platform management buses between a central Baseboard Management Controller (BMC) and various satellite management controllers (SMCs) is disclosed.
Abstract: A star Intelligent Platform Management Bus (“IPMB”) topology that uses independent intelligent platform management buses between a central Baseboard Management Controller (“BMC”) and various satellite management controllers (“SMCs”) is disclosed. An SMC is any management controller that is not the central BMC. Thus, an SMC may or may not include BMC functionality. The star IPMB topology provides fault isolation such that if a satellite controller fails in a way that corrupts the IPMB to which it is connected, communication is only lost with the failed controller. In addition, the star IPMB topology offers separate address domains whereby multiple controllers can potentially have the same address. The star IPMB topology further offers multiple owner security by isolating each module so that a module's controller can only directly communicate with the central BMC for the chassis.

Patent
15 Oct 2002
TL;DR: In this article, a transfer switching apparatus is used to switch from one or more of the AC input buses to the distribution bus, with a fast transfer switch used to interrupt the supply of power from the input buses, during switching of the input switches.
Abstract: Dual feed power supply system provides high reliability of a dual utility feed, with minimal interruptions in power supplied to critical loads during switching, and compensation for voltage sags occurring on the primary power feed. AC input buses are connected through a transfer switching apparatus to phase lines of a distribution bus. The transfer switching apparatus has a first input terminal connected to one of the phase lines of the first input bus and a second input terminal connected to one of the phase lines of the second input bus, and an output terminal connected to one of the phase lines of the distribution bus. Input switches allow switching from one or the other of the AC input buses to the distribution bus, with a fast transfer switch used to interrupt the supply of power from the input buses to the distribution bus during switching of the input switches.

Patent
24 May 2002
TL;DR: In this paper, a computer system (100) configured with an optical bus architecture is described, which includes a processing unit (102) in electrical communication with a first optical bus interface.
Abstract: A computer system (100) configured with an optical bus architecture is disclosed herein. The computer system (100)includes a processing unit (102) in electrical communication with a first optical bus interface.(104) The computer system further includes a functional device (118) in electrical communication with a second optical bus interface.(110c) An optical communication channel (106) extends between the first optical bus interface (104) and the second optical bus interface.(110c)

Patent
06 Jun 2002
TL;DR: In this paper, a protocol selector unit is used to select a bus protocol I/O unit to communicate with the device over the universal bus, and the bus protocol unit communicates over the bus by using a protocol that is compatible with a device.
Abstract: A universal bus communicates information by one of plural bus protocols. A bus protocol selector is operable to select one of the plural bus protocols associated with a device interfaced with an information handling system and to communicate information over the bus with the selected bus protocol. An Input/Output chip includes a protocol selector unit that selects a bus protocol I/O unit to communicate with the device over the universal bus. The bus protocol I/O unit communicates over the universal bus by using a bus protocol that is compatible with the device. For instance, the one of plural available differential serial bus protocols is selected so that the bus protocol I/O unit communicates with the device using a bus protocol compatible with the device. In some instances, a bypass circuit configures the physical characteristics of the universal bus, such as by interfacing or removing a capacitor with the universal bus to support AC or DC coupled bus protocols.

Patent
09 May 2002
TL;DR: The virtual host bus adapter (VHBA) as mentioned in this paper is a hardware-emulation module that makes the VHBA appear to operating system environments as a conventional HBA with dedicated hardware.
Abstract: Accessing some storage-area networks (SANs) requires a client computer to include a special electronic component, known as a host bus adapter (HBA). However, the present inventor recognized that conventional host bus adapters add considerable expense to the cost of accessing the storage-area network. Accordingly, the present inventor devised a host bus adapter that is implemented in software and thus referred to as a “virtual” host bus adapter. One exemplary embodiment of the virtual host bus adapter includes a hardware-emulation module that makes the virtual host bus adapter appear to operating system environments as a conventional host bust adapter with dedicated hardware.

Patent
12 Jul 2002
TL;DR: In this paper, a system for monitoring information real-time through a network is presented, where the mediator is adapted to receive events from any one of the network elements as the call as being routed through the elements from the source to the destination.
Abstract: A system for monitoring information real-time through a network. The system has a plurality of network elements Each of the network elements comprises an interface device. The plurality of network elements are configured to route a call from a source to a destination through the network elements. A mediator is coupled to each of the network elements. The mediator is adapted to receive events from any one of the network elements as the call as being routed through the elements from the source to the destination. A message bus is coupled to the mediator for receiving the events. The system also has an application process coupled to the messaging bus. The application process is adapted to use the events. The system is fault tolerant and information under process is not lost even when one of the system components fails.

Patent
18 Nov 2002
TL;DR: In this paper, a router for directing messages across a bus in a telecommunications system is described. The router comprises a bus interface and a processor, and it is coupled to the bus and is operable to receive routing request in a common format from the bus, where the routing request comprising a destination device address.
Abstract: A router for directing messages across a bus in a telecommunications system. The router comprises a bus interface and a processor. The bus interface is coupled to the bus and is operable to receive routing request in a common format from the bus, where the routing request comprising a destination device address. The processor is coupled to the bus interface and is operable to receive the routing request from the bus interface and determine routing information based on the destination device address.

Patent
14 Feb 2002
TL;DR: In this paper, a clock distribution system for an integrated circuit comprising a plurality of regions (1, 2, 3) connected by a communications bus is presented, where a predetermined clock insertion delay (20a, 20b, 20c, 22a, 22b, 22c) is inserted in each functional block and bus node.
Abstract: A clock distribution system for an integrated circuit comprising a plurality of regions (1, 2, 3) connected by a communications bus (12). Each region comprises a functional block (10a, 10b, 10c) and at least one bus node (14a, 14b, 14c) for connecting a respective functional block to the communications bus (12). A distributed clock signal (16) is allowed to skew between regions, but synchronised within respective regions. A predetermined clock insertion delay (20a, 20b, 20c, 22a, 22b, 22c) is inserted in each functional block and bus node.

Patent
08 Apr 2002
TL;DR: In this paper, the authors consider a communications system with a plurality of communications buses, at least one bus device connected to the plurality of communication buses, and at least two bus controllers.
Abstract: A communications system may include a plurality of communications buses, at least one bus device connected to the plurality of communications buses, and a plurality of bus controllers for sending a plurality of bus enable signals to the at least one bus device. The at least one bus device may include selection circuitry for selecting one of the communications buses based upon the plurality of bus enable signals while being tolerant of an error on at least one of the bus enable signals. First and second bus enable signals may have a same value and may be generated by a primary bus controller upon receiving power. A third bus enable signal may be generated by a redundant bus controller upon receiving power.

Journal ArticleDOI
04 Jul 2002-Sensors
TL;DR: The new intra-module multi-element microsystem (IM 2 ) bus is nine-line interface with 8b serial data which implements several advanced features such as power management and plug-n-play while maintaining minimum hardware overhead at the sensor node.
Abstract: This paper overviews existing digital communication buses which are commonly used in sensor networks, discusses sensor network architectures, and introduces a new sensor bus for low power microsystem applications. The new intra-module multi-element microsystem (IM 2 ) bus is nine-line interface with 8b serial data which implements several advanced features such as power management and plug-n-play while maintaining minimum hardware overhead at the sensor node. Finally, some issues in wireless sensor networking are discussed. The coverage of these issues provides a guideline for choosing the appropriate bus for different sensor network applications. Keywords: Sensor bus, Sensor network, Microsystem architecture, Wireless sensor networks Introduction The advances in sensor technologies, including Micro-Electro-Mechanical Systems (MEMS), and associated interfaces, signal processing and networking have made it possible to construct highly functional “smart” sensors and to connect a large number of sensors for distributed measurement and control applications. The networking of many smart sensors enables high quality detection/measurement networks with low cost and easy deployment, and it provides new monitoring and control capability for a wide range of applications, such as industrial process monitoring, health care, environmental oversight, safety and security. In a sensor network, sensors are generally connected to a microcontroller which provides built-in linearization, error correction, and the access to the network. The interface between the sensor node

Journal ArticleDOI
TL;DR: A theoretical and an experimental study on the problem of scheduling the processing of a very large size image on a cluster of processors interconnected via a bus network using the divisible load paradigm, referred to as DLT, to schedule the entire processing of an image onto the processors.

Patent
30 Oct 2002
Abstract: A data processing system (100) comprises a system bus (120), a plurality of devices (110, 150, 160, 170) coupled to the system bus (120), a bus monitor circuit (140), and a clock generator (130). The plurality of devices (110, 150, 160, 170) includes at least one bus master (110, 150) which is capable of performing accesses on the system bus (120). The bus monitor circuit (140) is coupled to the at least one bus master (110, 150), and has an output for providing a bus idle signal to indicate that no bus master is attempting to perform an access on the system bus (120). The clock generator (130) has an output coupled to at least one of the plurality of devices (110, 150, 160, 170) and provides a bus clock signal having a first frequency when the bus idle signal is inactive and having a second frequency lower than the first frequency when the bus idle signal is active.

Patent
26 Apr 2002
TL;DR: In this article, a system for maintaining proper termination and error-free communicaton in a network bus (12) including a power bus includes at least one network device (18), a network controller (16), and at least on bus protection element.
Abstract: A system for maintaining proper termination and error-free communicaton in a network bus (12) including a power bus includes at least one network device (18), a network controller (16) and at least on bus protection element. The network devices (18) are electrically connected to and adapted to communicate via the network bus (12). The network controller (16), in turn, is electrically connected to the network bus (12) and is adapted to direct communicaitons with the network devices (18) via the network bus (12). The network controller (16) is also adapted to provide power signals to the network devices (18) via the power bus of the network bus (12). The network controller (16) and/or the bus protection elements can monitor signals on the network bus (12). And based upon the network controller (16) and/or bus protection elements identifying a predefined number of improper signals, the bus protection elements can selectively connect and disconnect respective network devices (18) to and from the network.

Journal ArticleDOI
TL;DR: These strategies are shown to provide a complete flexibility in tuning the number of installments that can be used per load during the distribution process so as to meet the objective of scheduling multiple divisible loads on bus networks.

Patent
03 Jun 2002
TL;DR: In this article, a method and system for a virtual local network to span multiple loop free network topology domains is provided, where a network architecture comprises a plurality of nodes connected by paths, a first physical broadcast domain and a second physical broadcast domains each comprising a separate subset of the plurality, and a logical broadcast domain comprising a node from each subset.
Abstract: A method and system is provided for a virtual local network to span multiple loop free network topology domains. According to one aspect of the invention, a network contains at least two loop free network topology domains and a virtual local area network spanning at least a portion of each of the two domains. According to one aspect of the invention, a network architecture comprises a plurality of nodes connected by paths, a first physical broadcast domain and a second physical broadcast domain each comprising a separate subset of the plurality of nodes, and a logical broadcast domain comprising a node from each subset.