Showing papers on "Bus network published in 2003"

Port adapter for high-bandwidth bus

Abstract: A port adapter for connecting zero or more network interfaces to a host system having a SPI-4 bus is disclosed. The port adapter comprises zero or more network interfaces; a SPI-4 bus coupled to a host system to provide a communication channel between the host and the network interfaces; a control bus coupled to the host system for controlling and monitoring the port adapter; and interface logic that interfaces the SPI-4 bus and the control bus to the network interfaces. Methods are provided for selecting and using one of a small plurality of different packet formats for various networking technologies, so that the port adapter can hide details of the technology that it handles from the host system, and for operating the host system's SPI-4 bus at one of several speeds based on bandwidth requirements of the port adapter.

Apparatus, system, and method for bus link width optimization

Abstract: A bus permits the number of active serial data lanes of a data link to be re-negotiated in response to changes in bus bandwidth requirements In one embodiment, one of the bus interfaces triggers a re-negotiation of link width and places a constraint on link width during the re-negotiation

Distributed architecture for real-time coordination of bus holding in transit networks

Abstract: A distributed control approach based on multiagent negotiation is presented, wherein stops and buses act as agents that communicate in real-time to achieve dynamic coordination of bus dispatching at various stops. The negotiation between a Bus Agent and a Stop Agent is conducted based on marginal cost calculations. We present optimality conditions for the formulated problem, using a negotiation algorithm, which we derive, to coordinate bus holding at various stops. A comparison between the negotiation algorithm and other simple bus control strategies such as on-schedule and even-headway strategies made through simulations verifies the robustness and efficiency of our negotiation strategy to different transit environments, involving both stationary passenger arrivals as well as a variety of nonstationary passenger arrivals.

Robotic tool coupler rapid-connect bus

Abstract: A tool changer comprising a master module and a tool module includes a rapid-connect communication bus between the master and tool modules. A unique tool identification number, along with other tool-related information, may be transmitted from the tool module to the master module within about 250 msec of the master and tool modules coupling together. The master module includes a robotic system communications network node connected to the rapid-connect communication bus, and operative to transmit data between the tool and the network via the communication bus. The need for a separate network node in the tool module is obviated, reducing cost and reducing the start-up time required to initialize such a network node upon connecting to a new tool. The rapid-connect communication bus may be a serial bus.

Arrayed data storage architecture with simultaneous command of multiple storage media

Abstract: A storage system controller (302) includes a plurality of media controllers (301), a local microprocessor (306), and a host interface logic (310), operably coupled by a multi-drop parallel bus. The multi-drop parallel bus (319) includes a control bus (324), a payload data bus (320), a real-time ready-status (data ready) signaling bus (322) and a general microprocessor bus (330). Each media controller has a storage media (311) operably coupled thereto. Each media controller includes a parameter storage (404), a media interface circuit (406), a control data state machine (408), a command sequencer state machine (410), a media-side multi-mode transfer state machine (412), a dual-port memory (402), a memory controller (420), and a host-side transfer state machine (430). The host interface logic and the media controllers are implemented in one or more Field Programmable Gate Arrays. The storage system architecture allows the microprocessor to simultaneously broadcast a command to the media controllers, which have a capability to substantially simultaneously begin exchanging data with the storage media in response to the command. The storage system has provision for Redundant Array of Independent Disks, method 0, operation.

Modular wireless integrated network sensor (WINS) node with a dual bus architecture

Abstract: A modular sensing station architecture that supports flexible power management includes one or more sensors connected to a WINS node. Each node includes power supply, data acquisition, programmable microprocessor and wireless transceiver modules that communicate data and instructions over a bus. The bus suitably includes a signal bus for communicating instructions and low bandwidth data and a high-capacity data bus for transferring high bandwidth data and executing high power tasks. The dual bus approach provides constant communications among the modules and low-capacity data transfer with the option to activate the high-power circuits or tasks only as needed.

Multiple channel modules and bus systems using same

Abstract: Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.

Evaluation of fault handling of the time-triggered architecture with bus and star topology

Abstract: Arbitrary faults of a single node In a time-triggered architecture (TTA) bus topology system may cause error propagation to correct nodes and may lead to inconsistent system states. This has been observed in validation work using software implemented fault injection (SWIFI) and heavy-ion fault injection techniques in a TTA cluster. In a TTA system, the membership and the clique avoidance algorithms detect state inconsistencies and force the nodes that do not have the same state with the state of majority of nodes, to restart. Changing the interconnection structure of the cluster to a star topology allows the use of star couplers that will isolate faults of a node, thus guaranteeing consistency, even in the presence of arbitrary node failures. The same SWIFI and heavy-ion fault injection experiments that caused error propagation in bus-based TTA clusters, were performed in the star configuration. No error propagation was observed in a TTA system with the star topology during the execution of SWIFI and heavy-ion experiments.

Bus structure for power switching circuits

Abstract: A bus system is disclosed for use with switching devices, such as power electronic devices. The system includes generally parallel bus elements that define electrical reference planes, such as for a dc bus. The bus elements are separated from one another by insulative layers, with additional insulative layers being available for separating the system from other circuit components. Portions of the bus elements are extended or exposed to permit connection to the circuit elements, including packaged switching circuits and energy storage or filtering circuits. The bus system may be conformed to a variety of geometric configurations, and substantially reduces parasitic inductance and total loop inductance in the resulting circuitry.

Combining wire swapping and spacing for low-power deep-submicron buses

Abstract: We propose an approach for reducing the energy consumption of address buses that targets both the switching and the crosstalk components of power dissipation.The method is based on the combined application of two techniques. First, selective wire swapping is applied in such a way that bus wires with high coupling activity are kept far away from each other. Then, the slack available in the floorplanning for the routing of the bus wire is exploited to realize a bus with non-uniform inter-wire spacing. Both swapping and placement are driven by the switching data obtained from the analysis of typical address bus traces, and can be successfully applied to any address bus.Results on a set of profiled address streams show the effectiveness of the proposed approach.

Bus station with integrated bus monitor function

Abstract: Described is a bus station (e.g., a sensor, an actuator, a gateway) which performs a primary device function and a secondary function (e.g., a bus monitor function). To perform the secondary function, the bus station is equipped with a bus monitor arrangement which allows the bus station to access, to detect and to further process telegram traffic carried on the bus system. Also described is a network equipped with a plurality of such bus stations and a method for carrying out such monitoring with the aid of the bus stations.

Integrated network switching hub and bus structure

Abstract: A network switching hub is implemented on an IC chip, and has a bus connected to external ports through sets of queue switch transistors, source to drain for data switched onto the bus, the queue switch transistors gated simultaneously by control lines from an on-board arbitrator controller following a preprogrammed arbitration scheme. Data is switched off the bus and hub by port adapter controllers connected to read amplifier receivers connected directly to the on-chip bus, the port adapter controllers enabled by the arbitrator controller following the same preprogrammed arbitration scheme. Ports may be serial or parallel, and may be adapted to special purposes, such as PCI and hub to hub connection for expansion.

Bus connection system

Abstract: A bus station in the form of a hardware dongle, operates in conjunction with a USB Device running suitable software. When the bus station determines that a bus host is connected to a first bus communication port thereof, it acts as a transceiver to allow conventional bus communications between said bus host and a bus device connected to a second bus communication port thereof. When the bus station determines that a bus device running suitable software is connected to the first bus communication port thereof, it acts as an alternate host to allow bus communications between said bus device connected to the first bus communication port and a bus device connected to a second bus communication port.

Direct memory access controller system

Abstract: A data transfer system comprising a first bus interface (120), a second bus interface (106), a first-in-first-out memory (105A-105N), a controller (102) and a message unit (108). The message unit (108) is operable to queue a plurality of data transfer request messages from the first bus interface (120) and the second bus interface (106). The controller (102) is operable to process each data transfer request message and transfer data between the first bus interface (120), the first-in-first-out memory (105A-105N) and the second bus interface (106). The controller (102) is configured to calculate error detection codes (EDCs) and chain EDC values.

Expandable slave device system

Abstract: A bus system for use with addressable memory has a global bus of bidirectional signal lines. The global bus has a first end and a second end. A master device transmits data to and receives data from the global bus at the first end. A global bus terminator is coupled to the global bus at the second end. One or more slave devices, including a last slave device at a furthest distance from the master device, each includes an active terminator coupled to at least some of the bidirectional signal lines of the global bus. The active terminator of only the last slave device is enabled.

Design theory and implementation for low-power segmented bus systems

Abstract: The concept of bus segmentation has been proposed to minimize power consumption by reducing the switched capacitance on each bus [Chen et al. 1999]. This paper details the design theory and implementation issues of segmented bus systems. Based on a graph model and the Gomory-Hu cut-equivalent tree algorithm, a bus can be partitioned into several bus segments separated by pass transistors. Highly communicating devices are placed to adjacent bus segments, so most data communication can be achieved by switching a small portion of the bus segments. Thus, a significant amount of power consumption can be saved. It can be proved that the proposed bus partitioning method achieves an optimal solution. The concept of tree clustering is also proposed to merge bus segments for further power reduction. The design flow, which includes bus tree construction in the register-transfer level and bus segmentation cell placement and routing in the physical level, is discussed for design implementation. The technology has been applied to a μ-controller design, and simulation results by PowerMill show significant improvement in power consumption.

SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips

Abstract: A high performance communication architecture, SAMBA-bus, is proposed in this paper. In SAMBA-bus, multiple compatible bus transactions can be performed simultaneously with only a single bus access grant from the bus arbiter. Experimental results show that, compared with a traditional bus architecture, the SAMBA-bus architecture can have up to 3.5 times improvement in the effective bandwidth, and up to 15 times reduction in the average communication latency. In addition, the performance of SAMBA-bus architecture is affected only slightly by arbitration latency, because bus transactions can be performed without waiting for the bus access grant from the arbiter. This feature is desirable in SoC designs with large numbers of modules and long communication delay between modules and the bus arbiter.

Automatic addressing on bus systems

Abstract: The invention relates to a method for automatically allocating addresses to control devices (3-6) in a means of communication, which are connected to a bus system (1). According to said method, the control devices (3-6) exchange data via a common data bus line (2) by means of transmitting/receiving units (10) and simultaneously access the data transmitted by means of the common data bus line (2). Also disclosed is a bus system (1) for carrying out the inventive method. The aim of the invention is to create a method and a bus system which optimize automatic address allocation in a bus system comprising a common data line. Said aim is achieved by starting an address allocation interval by means of a message on the common data bus line (2). The common data bus line (2) is then galvanically separated into individual partial sections within the address allocation interval based on said message, the control devices (4-6) that are to be addressed galvanically separating the common data bus line (2) by means of a separating means (9). In addition, the control devices (4-6) that are to be addressed set the respective transmitting unit (10) thereof to a certain transmission potential.

Realistic bus route model considering the capacity of the bus

Abstract: This paper investigates the bus route behavior using a more realistic cellular automaton model in which the bus capacity is considered. It is shown that with the introduction of bus capacity, four new states appear compared with the previous works. The results enable us to conclude that the efficiency of the bus route system cannot be enhanced simply through increasing the number of buses. Moreover, it is pointed out that a proper value of the bus capacity can lead to the optimal configuration of the bus system.

Low power system and method for a data processing system

Abstract: Systems and methods are discussed to identify a recoverable state in a low power device. A low power device (100, 300, or 400) having an arbiter (110, 310, or 410) to grant system bus access to a plurality of bus masters is set to initiate a low power mode of operation. A low power controller (150, 350, or 450) within the low power device provides a request to the bus arbiter to initiate a low power mode. The bus arbiter stops granting bus requests to the bus masters and identifies when the system bus has processed all current bus accesses. When the system bus is idle, the bus arbiter returns a bus grant signal to the low power controller. Clocks associated with the bus masters are disabled to suspend the bus arbiters and allow less power to be consumed by the low power device.

Scheduling Divisible Loads with Processor Release Times and Finite Size Buffer Capacity Constraints in Bus Networks

Abstract: In this paper we address the problem of processing a computationally intensive divisible load with high memory requirements on a bus network. Each network node is assumed to have a limited memory capacity (buffer space), while at the same time being available for processing after a specific time (release time). The combined influence of the release times, as well as the limited buffer capacity available, is considered in the problem formulation, with the objective to minimize the overall processing time of the divisible load. In the existing literature, these two issues have been considered independently, although in practice, they are commonly found to coexist. The Multi-Installment Balancing Strategy (MIBS) presented in this paper, manages to address both of these constraints by building on-top of the analytical solutions derived by a buffer capacity-unaware approach. MIBS monitors the available resources and adapts the processing and communication phases according to their availability. Towards this goal both single and/or multi-installment scheduling is utilized. The description of the algorithms accompany simulation experiments that highlight the behavior of MIBS. It should be stressed that the use of MIBS allows the processing of loads that exceed by far the total memory capacity of the available machines, while at the same time exhibiting processing times that match the ones predicted by strategies that ignore the memory constraints.

Controller for controlling routers

Abstract: A controller for controlling a plurality of network nodes in a communications network is disclosed. The controller is arranged to define a group of network, nodes to be monitored based on a value of one or more attributes of said network nodes. The network nodes may be routers.

Silicon object array with unidirectional segmented bus architecture

Abstract: A logic array is provided, which includes a plurality of unidirectional segmented buses connecting a plurality of processing elements, called silicon objects, within an integrated circuit. The bus includes a string of unidirectional bus segments. Each silicon object includes a bus input coupled to one of the bus segments in the first bus, and a bus output coupled to a next subsequent one of the bus segments in the first bus. A landing circuit is coupled to the bus input for receiving digital information from the bus input. A function-specific logic block is coupled to an output of the landing circuit and has a result output. Each silicon object further includes a multiplexer having first and second inputs coupled to the bus input and the result output, respectively, and having an output coupled to the bus output.

The efficient bus arbitration scheme in SoC environment

Abstract: This paper presents the dynamic bus arbiter architecture for a system on chip design. The conventional bus-distribution algorithms, such as the static fixed priority and the round robin, show several defects that are bus starvation, and low system performance because of bus distribution latency in a bus cycle time. The proposed dynamic bus architecture is based on a probability bus distribution algorithm and uses an adaptive ticket value method to solve the impartiality and starvation problems. The simulation results show that the proposed algorithm reduces the buffer size of a master by 11% and decreases the bus latency of a master by 50%.

Method and apparatus for border node behavior on a full-duplex bus

Abstract: A method and apparatus relating to the behavior of border nodes within a high performance serial bus system is disclosed. A method for determining and communicating the existence of a hybrid bus is disclosed. A method for determining a path to a senior border node is disclosed, as is a method for identifying a senior border node Various methods for properly issuing gap tokens within a beta cloud are disclosed.

Redundant control unit arrangement

Abstract: The invention relates to a control unit arrangement comprising a plurality of control units (1-3, 20-23) in a means of transport, said control units being networked by means of a first data bus (4). Said arrangement contains control units (1-3; 20-3) which are redundant in terms of a control function and a data bus disconnector (5) is associated with the redundantly embodied control units (1-- 3; 20-23), said disconnector connecting or disconnecting the data bus (4) according to an evaluation signal. In order to optimise the redundant arrangement, each of said data bus connectors (5) is connected to a signal line of at least one other redundant control unit (1-3; 20-23), another redundant control unit (2,3; 21; 23) transmits an evaluation signal to the data bus disconnector (5) associated with a first redundant control unit (1; 20; 22), the evaluation signal being the result of a functional test of the other redundant control unit (2,3; 21; 3) in terms of the first redundant control unit (1; 20; 22). The data bus disconnector (5) of the first redundant control unit (1; 20; 22) disconnects the data bus (4) according to the result of a logic circuit, at least one input signal of the logic circuit being formed by the at least one evaluation signal.

Configurable synchronous or asynchronous bus interface

Abstract: A system architecture and method allows for both synchronous and asynchronous communications on a common bus. Components that are able to reliably communicate via the bus using a synchronous interface are configured to communicate synchronously. Components that would require an unacceptable reduction in system-clock frequency to achieve synchronous communications are configured to communicate asynchronously. A bus controller facilitates bus arbitration, as well as synchronous-to-synchronous, synchronous-to-asynchronous and asynchronous-to-synchronous, and asynchronous-to-asynchronous transfers between components. To accommodate for physical layout dependencies, the components include a bus interface that is configurable for either synchronous or asynchronous communications, so that the determination of whether communications will be synchronous or asynchronous can be made after the layout is completed. The determination of whether a synchronous or asynchronous interface is used may also be dependent upon actual system performance, thereby facilitating a dynamic reconfiguration to optimize system performance.

The effect of start-up delays in scheduling divisible loads on bus networks: An alternate approach

Abstract: In this paper, scheduling of divisible loads in a bus network is considered. The objective is to minimize the processing time by including the overhead component due to start-up time that could degrade the performance of the system, in addition to the inherent communication and computation delays. These overheads are considered to be constant additive factors to the communication and computation components. A closed-form expression for optimal processing time is derived. Using this closed-form expression, this paper analytically proves significant results regarding the optimal sequence of load distribution and optimal number of processors. Numerical examples are presented to illustrate the analysis.

Bus controlled power switch

Abstract: A peripheral device (10) has a bus-controlled switching arrangement (40) for operating a power supply (60). The device comprises a bus interface (30) adapted for communicating with a remote device(20) via a bus(25). A switch circuit(40) is connected between the bus interface(30) and a power supply(60). The switch circuit(40) is operative, when the power supply(60) is in an inactive state, for sensing bus activity and for generating a signal for activating the power supply(60) in response to the sensed bus activity, wherein the switch circuit(40) has no power dissipation when no activity is sensed on the bus(25).