Showing papers on "Bus network published in 2004"

An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration

Abstract: In this paper we present a network interface for an on-chip network. Our network interface decouples computation from communication by offering a shared-memory abstraction, which is independent of the network implementation. We use a transaction-based protocol to achieve backward compatibility with existing bus protocols such as AXI, OCP and DTL. Our network interface has a modular architecture, which allows flexible instantiation. It provides both guaranteed and best-effort services via connections. These are configured via network interface ports using the network itself, instead of a separate control interconnect. An example instance of this network interface with 4 ports has an area of 0.143 mm/sup 2/ in a 0.13 /spl mu/m technology, and runs at 500 MHz.

The Intermittent Bus Lane signals setting within an area

Abstract: Intermittent Bus Lane (IBL) used for bus priority is a lane in which the status of a given section changes according to the presence or not of a bus in its spatial domain: when a bus is approaching such a section, the status of that lane is changed to BUS lane, and after the bus moves out of the section, it becomes a normal lane again, open to general traffic. Therefore when bus services are not so frequent, general traffic will not suffer much, and bus priority can still be obtained. This measure can be operating at a single city block, but if all related control parameters along bus lines are considered together, more time gains can be obtained. In this paper, the basic structure and operation of IBL around a single intersection are briefly introduced, then the construction of an objective function and its relationships with the related priority control parameters along one bus line and their simplifications are described. Finally the calculations of the priority control parameters when there are several connected bus lines within an area and some simulation results are discussed.

Distributed network organization and topology discovery in ad-hoc network

Abstract: A distributed network method for self-organizing a group of nodes into a bi-directional communication network where initially there is no central coordinator in the prospective network environment. The method involves engaging in the process of determining internodal communication capabilities en route to creating a network topology table, and then using that table as a guide (a) selecting, by nodal election, an appropriate central coordinator, and (b) establishing proxy nodes which enable full network bi-directional communication between all nodes, including otherwise communicatively-compromised hidden nodes.

Split computer architecture to separate user and processor while retaining original user interface

Abstract: A network interface is described in which a single computer bus is split over a long distance into two or more inter-communicating buses. On one bus, processing and applications are provided and on the other remote bus, peripheral and local controllers are provided. The buses communicate through a series of: bridge, FPGA, FPGA and bridge. Between the FPGAs, a communication path provides long distance communication.

Automated bus generation for multiprocessor SoC design

Abstract: The performance of a multiprocessor system heavily depends upon the efficiency of its bus architecture. This paper presents a methodology to generate a custom bus system for a multiprocessor system-on-a-chip (SoC). Our bus-synthesis tool, which we call BusSynth, uses this methodology to generate five different bus systems as examples: 1) bidirectional first-in first-out bus architecture; 2) global bus architecture (GBA) version I; 3) GBA version III; 4) hybrid bus architecture (Hybrid); and 5) split bus architecture. We verify and evaluate the performance of each bus system in the context of three applications: an orthogonal frequency division multiplexing wireless transmitter, an MPEG2 decoder, and a database example. Our methodology gives the designer a great benefit in the fast-design space exploration of bus architectures across a variety of performance impacting factors such as bus types, processor types, and software programming style. In this paper, we show that BusSynth can generate buses that, when compared to a typical general GBA, achieve superior performance (e.g., 41% reduction in execution time in the case of a database example). In addition, the bus architecture generated by BusSynth is designed in a matter of seconds instead of weeks for the hand design of a custom bus system.

Method and apparatus for sending data from multiple sources over a communications bus

Abstract: In a memory system, multiple memory modules communicate over a bus. Each memory module may include a hub and at least one memory storage unit. The hub receives local data from the memory storage units, and downstream data from one or more other memory modules. The hub assembles data to be sent over the bus within a data block structure, which is divided into multiple lanes. An indication is made of where, within the data block structure, a breakpoint will occur in the data being placed on the bus by a first source (e.g., the local or downstream data). Based on the indication, data from a second source (e.g., the downstream or local data) is placed in the remainder of the data block, thus reducing gaps on the bus. Additional apparatus, systems, and methods are disclosed.

Methods and apparatus for synchronizing devices on different serial data buses

Abstract: The invention provides a method of synchronizing one or more devices on a first bus with one or more devices on a second bus. The method comprises acquiring timing information from the first bus and the second bus, determining a timing offset between the first bus and the second bus, and, broadcasting the timing offset to the one or more devices on the second bus so that the one or more devices on the second bus can adjust their timing to be synchronized with the one or more devices on the first bus.

Methods and apparatus for enabling bus connectivity over a data network

Abstract: A method and system for interconnecting peripherals, processor nodes, and hardware devices to a data network to produce a network bus providing OS functionality for managing hardware devices connected to the network bus involves defining a network bus driver at each of the processor nodes that couples hardware device drivers to a network hardware abstraction layer of the processor node. The network bus can be constructed to account for the hot-swappable nature of the hardware devices using a device monitoring function, and plug and play functionality for adding and, removing device driver instances. The network bus can be used to provide a distributed processing system by defining a shared memory space at each processor node. Distributed memory pages are provided with bus-network-wide unique memory addresses, and a distributed memory manager is added to ensure consistency of the distributed memory pages, and to provide a library of functions for user mode applications.

Single wire bus for connecting devices and methods of operating the same

Abstract: A master/slave system architecture including a single wire bus and master device and bus interface coupled to the bus. The system further includes slave devices having respective bus interfaces coupled to the bus. The system further includes a communication protocol implemented over the single wire bus and employed by the master and the slave devices. The protocol includes bus transactions for communicating between the master and the slave devices. The communication protocol further includes Master Slave Operational Interface (MSOI) that includes repertoire of functions properties stored in the master device, whereby, the master can communicate with any slave device that supports functions properties that belong to the repertoire of functions properties, using the bus transactions, substantially without need of retrofit.

Modular sensor network node

Abstract: A distributed wireless sensor network node is disclosed. The wireless sensor network node includes a plurality of sensor modules coupled to a system bus and configured to sense a parameter. The parameter may be an object, an event or any other parameter. The node collects data representative of the parameter. The node also includes a communication module coupled to the system bus and configured to allow the node to communicate with other nodes. The node also includes a processing module coupled to the system bus and adapted to receive the data from the sensor module and operable to analyze the data. The node also includes a power module connected to the system bus and operable to generate a regulated voltage.

System, method and storage medium for providing a serialized memory interface with a bus repeater

Abstract: A packetized cascade memory system including a plurality of memory assemblies, a memory bus including multiple segments, a bus repeater module and a segment level sparing module. The bus repeater module is in communication with two or more of the memory assemblies via the memory bus. The segment level sparing module provides segment level sparing for the communication bus upon segment failure.

Optical network topology databases and optical network operations

Abstract: A number of wavelength division multiplexing (WDM) access nodes employ a distributed search based scheme to build network topology databases based on a set of connectivity constraints (1230). A set of one or more connectivity constraints that include quality or service (QoS) based criteria are applied on a physical network topology of a WDM optical network to divide that optical network into separate service levels (910) whose topologies (920) are determined for each of the service levels. A number of WDM access nodes of an optical network employ a source based scheme to establish communication paths (1145). Each of these access nodes stores a set of one or more network topology databases based on a set of connectivity constraints. Each of these nodes employs a messaging scheme to propagate notification of changes in the optical network to other nodes to maintain their databases.

Command transmission method and command transmission apparatus in pipeline bus system

Abstract: A command transmission method and apparatus, capable of improving command transmission efficiency by using a queue, when the queue is required during an operation of a command bus in a pipeline bus system includes determining whether a command bus of the pipeline bus system is in a busy state; and transmitting a command from the master to a target slave while selectively using a queue protocol of an arbiter of the pipeline bus system according to a result of the determination

Safety system for an elevator structure

Abstract: Disclosed is a safety system (10) for an elevator structure, comprising a control unit (11), a bus node (13), a safety element (16), and a bus (12) for enabling communication between the control unit (11) and the bus node (13). The bus node (13) is provided with first circuitry means (14) which impinge the safety element (16) with a first analog signal upon a digital input by the control unit (11). The bus node (13) is also provided with second circuitry means (15) which pick up an analog signal on the safety element (16) and supply digital feedback data to the control unit (11) via the bus (12).

Multi-port system and method for routing a data element within an interconnection fabric

Abstract: The present invention relates generally to a generic fabric interconnect system and method for providing a data path between and among nodes and processing elements within an interconnection fabric. More specifically, there is provided a device accessible by a host processor for expanding access over a first bus to a second bus, the first bus and the second bus each being adapted to separately connect to respective ones of a plurality of bus-compatible devices, each device which comprise a link, a first circuit adapted to couple between the first bus and the link, and a second circuit adapted to couple between the link and the second bus, the first circuit and the second circuit each being operated as a bridge and being operable to (a) send outgoing information serially through said link in a form different from that of the first bus and the second bus (b) approve an initial exchange between the first bus and the second bus in response to pending bus transactions having a characteristic signifying a destination across a device, and (c) allow the host processor, communicating through the first bus, to individually address different selectable ones of the bus-compatible devices on the second bus: (i) using on the first bus substantially the same type of addressing as is used to access devices on the first bus, and (ii) without first employing a second, intervening one of the bus-compatible devices on the second bus.

Memory interface including an efficient variable-width bus

Abstract: A semiconductor device includes an interface controller for communication with a memory device over a communication link. The link includes a plurality of data lines for transmitting data. A plurality of bus width values are defined, each being a selectable number of data lines over which data are to be transmitted. The number of data lines is in the range between one and the number of the plurality of data lines. The interface controller is dynamically configurable to any of the defined bus width values, which becomes the current bus width. The transmission over each data line may be selectably in either direction. The transmission over all data lines corresponding to the current bus width may collectively carry, in at least one direction, command codes, memory addresses, and data in an intermixed manner.

Protective bus interface and method

Abstract: Method and apparatus are provided for preventing faulty commercial-off-the-shelf (COTS) peripherals or I/Os (68) from disabling the bus (62) to which they are connected. The apparatus has isolators (72) coupled to the bus (62) and the I/Os (68). A controller (86) is coupled between the interfaces, a processor (92) and memory (90), operating such that an I/O (68) cannot transfer data to the bus (62) without permission from the bus (62). Isolation memory keeps I/O (68) and bus (62) messages separate. I/O (68) messages are checked before being sent to the bus (62). The method comprises: determining if there is a message for the peripheral (36), temporarily storing the message, determining if the message is for output or input, and if for output, sending it to the peripheral (36), and if for input, requesting and receiving it from the peripheral (36), temporarily storing and checking it, and transferring it to the bus (62) only if valid. This prevents a failed I/O (68) or peripheral (36) from disabling the bus (62).

Sense mechanism for microprocessor bus inversion

Abstract: A sense mechanism for data bus inversion including a first memory device and an analog adder. The first memory device stores bits of the bus in a previous bus cycle. The analog adder compares the bits of the bus in the previous bus cycle with bits of the bus in a current bus cycle and provides a data inversion signal indicative of whether more than half of the bits of the bus have changed state. The analog adder operates as a bus state change sense device which rapidly evaluates bus state changes from one bus cycle to the next. The data inversion signal is used for selectively inverting the data bits of the bus and indicating bus inversion according to data bus inversion operation, such as according to X86 microprocessor protocol.

CANcentrate: an active star topology for CAN networks

Abstract: Distributed embedded systems that require real-time performance need a network capable of deterministic access delay. CAN is one such network that became widespread in recent years due to its electrical robustness, low price, and priority-based access control. However, its use in safety-critical applications has been controversial due to dependability limitations that arise from its bus topology and non-guaranteed atomic broadcast. In this paper, we propose an active star topology that allows solving many of the limitations related to the first aspect by means of strong error confinement. Nodes are interconnected through an active hub that is fully compatible with existing CAN controllers. The paper compares bus and star topologies, analyzes related work and discusses the hub implementation and dependability properties.

Creation and use of virtual device drivers on a serial bus

Abstract: A node on a serial bus, preferably a device such as a personal computer (PC), can emulate other devices using virtual device drivers A PC connected to a 1394 bus exposes its CROM on the bus which presents an image to other nodes on the 1394 bus and describes the functional units supported by the node The CROM can be changed dynamically by adding unit directories to the CROM detailing peripherals connected to the PC The PC can then be enumerated as the connected device by other PCs on the bus The PC can emulate or morph itself into any desired device or even multiple devices at the same time The invention also allows a PC to create devices that don't yet exist on the bus The invention allows a user to create virtual device objects with device properties to have just in case a user plugs the particular device in to the PC

System for transmission of data on a bus

Abstract: A system for transmitting data between a transmitter and a receiver on a communication network connecting a number of components, especially in a motor vehicle, has a CAN transceiver which converts logic signals into bus data signals downstream of each transmitter A non-inductive symmetrical CAN filter is connected downstream of each CAN bus transceiver The CAN filter has at least two impedances and it is preferably implemented as an X2Y capacitor

Layout conscious bus architecture synthesis for deep submicron systems on chip

Abstract: System-level design has a disadvantage in not knowing important aspects about the final layout. This is critical for SoC, where uncertainties in communication delay by very deep submicron effects cannot be neglected. This paper presents a layout-aware bus architecture (BA) synthesis algorithm for designing the communication sub-system of an SoC. BA synthesis includes finding bus topology and routing individual buses, so that constraints like area, bus speed and length, are tackled at the physical level. The paper presents the BA automatically synthesized for a network processor and a JPEG SoC.

CT-bus: a heterogeneous CDMA/TDMA bus for future SOC

Abstract: CDMA interconnect is a new interconnect mechanism for future SoC. Compared to a conventional TDMA-based bus, a CDMA-based bus has better channel isolation and channel continuity. We introduce a new bus architecture called CT-bus, which mixes and takes strengths of both CDMA-based and TDMA-based interconnect schemes. A CT-bus gives designers the ability to cope with widely varying communication requirements. We propose a method and a tool to explore the mapping of heterogeneous traffic flows onto the CT-bus. Simulation results on a multimedia mobile phone system show that traffic flows mapped onto a CT-bus meet the latency requirements while the same traffic flows mapped onto a conventional TDMA-only bus violate these requirements.

Multi-processor module

Abstract: An apparatus comprises a plurality of logically independent processors, a system bus, and a cache control and bus bridge device in communication with the plurality of processors such that the cache control and bus bridge device is logically interposed between the processors and the system bus, and wherein the processors and cache control and bus bridge device are disposed in a module form factor such that the apparatus is a drop-in replacement for a standard single processor module.

Method of providing an interface to a plurality of peripheral devices using bus adapter chips

Abstract: A method of electrically coupling a central processing unit (CPU) of a network server to a plurality of network interface modules. The method comprises providing each of the plurality of network interface modules with a respective bus adapter chip to route an I/O bus having a first format from the central processing unit to a primary side of each of the plurality of bus adaptor chips and routing another I/O bus of the first format from a secondary side of each of the plurality of bus adapter chips to respective ones of the network interface modules. The bus adapter chips also provide for arbitered access along the I/O buses and isolation of the CPU from electrical disruption when one the network interface modules is removed.

Controller area network wake-up system and method

Abstract: A controller area network employs a CAN bus for facilitating CAN communications among a plurality of communication controllers switched to an active state. The controller area network further employs a CAN wake-up controller for switching one or more communication controllers to the active state in response to an application of a non-interfering communication biasing signal to said CAN bus. Upon a termination of the application of a non-interfering communication biasing signal to said CAN bus, the CAN wake-up controller switches the communication controller(s) to an inactive state for impeding CAN communications by communication controller(s) via the CAN bus.

Multiple master buses and slave buses transmitting simultaneously

Abstract: A bus system, such as an internal bus system located within a digital device, is disclosed herein. The bus system comprises a plurality of master buses, each master bus connected to at least one master. The bus system also comprises a multi-bus interface connected to the plurality of master buses and a slave bus connected to the multi-bus interface. The multi-bus interface enables one master bus at a time to access the slave bus. Also disclosed herein are bus structures and methods for interfacing between master buses and slave buses.

Dynamic access scheduling memory controller

Abstract: Bus transactions in a memory controller are scheduled by storing a set of configuration parameters that define a bus scheduling policy, generating values of a set of dynamic cost functions for each bus transaction, ordering the bus transactions in accordance with the bus scheduling policy to produce ordered bus transactions and generating a memory transaction that is derived from the ordered bus transactions. The memory controller includes one or more control registers for storing the set of configuration parameters, a bus interface operable to capture bus transactions from applications, a set of buffers operable to store the bus transactions and the set of dynamic cost functions and one or more registers operable to store the statistical data and a cost policy. The memory controller selects the order of the bus transactions based on an arbitration and selection policy and generates memory transactions to an external memory.

Market based transmission expansion planning: stakeholders' desires

Abstract: In unbundled power markets, stakeholders have different interests and expectations from performance and expansion of the system. This paper presents a new market based approach for transmission expansion planning with consideration given to the stakeholders' desires using fuzzy decision making. Five groups of stakeholders; power producers, demand customers, system operator, network owners, and regulator, are considered. Competition, reliability, flexibility, network charge and environmental impacts are evaluated from the viewpoint of different stakeholders for selecting the final plan. Some market based criteria are presented to measure stakeholders' desires. The approach is applied to IEEE 30 bus network.

System, method and program product for extending range of a bidirectional data communication bus

Abstract: A communication system, method and program product are provided for establishing an extended bidirectional communication bus between a first device and a second device. The communication system includes decomposition logic for decomposing a single line, bidirectional data communication bus into a unidirectional transmit data communication bus and a unidirectional receive data communication bus. A differential communication subsystem is connected to the two unidirectional buses for extending the length thereof, and recomposition circuitry is connected to the differential communication subsystem for recombining the extended unidirectional transmit data communication bus and the extended unidirectional receive data communication bus to reestablish the single line, bidirectional data communication bus. The decomposition logic, differential communication subsystem and recomposition circuitry are implemented transparent to the first device and the second device and without use of a data direction control line.