Showing papers on "Bus network published in 2006"

Device and a method for communicating in a network

Abstract: A method of managing a communication network comprising a control plane and a network plane, the network comprising nodes and physical connections of the nodes, each of a plurality of nodes being a logical network device, supporting a control plane portion in the control plane and a network plane portion in the network plane, in which method, the control plane portions of the logical network devices form a logical network in a peer to peer fashion, and control data necessary for administering the communication network and/or for managing users of the communication network is contained in at least one database distributed between at least a plurality of control plane portions of the network devices forming the logical network.

Multi-protocol bus device

Abstract: In one general aspect, methods and devices for use with multiple communications protocols automatically determine which communications protocol to use when connected to a system bus. Signals transmitted on the system bus are monitored to determine what communications protocol the system bus is using. After determining which communications protocol the system is using, a compatible communications protocol is selected from one of several communications protocols stored in a device's memory. As a result, a user may connect a device to the system bus without having to determine which communications protocol is used by the system bus. Furthermore, suppliers may stock a single type of device that is compatible with multiple communications protocols reducing overhead associated with stocking devices. In addition, a device may be switched between systems without regard to the communications protocol of the device or system.

A hybrid SoC interconnect with dynamic TDMA-based transaction-less buses and on-chip networks

Abstract: The two dominant architectural choices for implementing efficient communication fabrics for SoC's have been transaction-based buses and packet-based networks-on-chip (NoC). Both implementations have some inherent disadvantages - the former resulting from poor scalability and the transactional character of their operation, and the latter from inconsistent access times and deterioration of performance at high injection rates. In this paper, we propose a transaction-less, time-division-based bus architecture, which dynamically allocates timeslots on-the-fly - the dTDMA bus. This architecture addresses the contention issues of current bus architectures, while avoiding the multi-hop overhead of NoC's. It is compared to traditional bus architectures and NoC's and shown to outperform both for configurations with fewer than 10 PE's. In order to exploit the advantages of the dTDMA bus for smaller configurations, and the scalability of NoC's, we propose a new hybrid SoC interconnect combining the two, showing significant improvement in both latency and power consumption.

An active star topology for improving fault confinement in CAN networks

Abstract: The controller area network (CAN) is a field bus that is nowadays widespread in distributed embedded systems due to its electrical robustness, low price, and deterministic access delay. However, its use in safety-critical applications has been controversial due to dependability limitations, such as those arising from its bus topology. In particular, in a CAN bus, there are multiple components such that if any of them is faulty, a general failure of the communication system may happen. In this paper, we propose a design for an active star topology called CANcentrate. Our design solves the limitations indicated above by means of an active hub, which prevents error propagation from any of its ports to the others. Due to the specific characteristics of this hub, CANcentrate is fully compatible with existing CAN controllers. This paper compares bus and star topologies, analyzes related work, describes the CANcentrate basics, paying special attention to the mechanisms used for detecting faulty ports, and finally describes the implementation and test of a CANcentrate prototype.

Smart Bicycles in an Urban Area: Evaluation of a Pilot Scheme in London

Abstract: Automated or smart bicycle systems are seen as a way to enhance mobility and provide a convenient access and egress mode for public transport. This paper summarizes an evaluation of a pilot system introduced in the London Borough of Hammersmith and Fulham in August 2004. Underground and commuter rail stations, as well as a heavily-used bus network, serve this densely populated area. A survey of users was conducted and data was collected from actual use of the system. Analysis of this data gave insights into the capabilities of these types of systems to enhance existing public transport services. In particular, it was found that the potential of the system lies primarily with leisure and recreational markets and with providing links to public transport stations. The pilot system included “sponsored” nonpaying users who tended to use the system more for commuting and utilitarian trips.

System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding

Abstract: A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an upstream data bus. The memory hub controller includes a receiver coupled to the upstream data bus and a transmitter coupled to the downstream data bus. Similarly, each of the memory modules includes a receiver coupled to the downstream data bus and a transmitter coupled to the upstream data bus. Each receiver includes a receive clock generator that is synchronized by coupling a known pattern of data to the receiver. The receiver determines which phase of the receive clock best captures the known pattern and uses that receive clock phase during normal operation.

Bus access arbitration scheme

Abstract: A bus arbitration scheme in a processing system. The processing system includes a bus, a plurality of processors coupled to the bus, and a bus arbiter. The bus arbiter may assign a first tier weight to each of the processors in a first tier, and a second tier weight to each of the processors in a second tier. The bus arbiter may sequentially grant bus access to the one or more processors during an initial portion of a bus interval based on the assigned second tier weights, and grant bus access to any one of the processors during the initial portion of the bus interval in response to a request from said any one of the processors having a first tier weight. When multiple processors are requesting access to the bus, the bus arbiter may grant bus access to the requesting processor with the highest weight in the highest tier.

Multi-port network interface device with shared processing resources

Abstract: A network interface device includes a bus interface that communicates over a bus with a host processor and memory, and a network interface, including at least first and second physical ports, which are coupled to send and receive data packets carrying data over a packet network. A protocol processor includes a single transmit processing pipeline and a single receive processing pipeline, which are coupled between the bus interface and the network interface so as to convey the data between both of the first and second physical ports of the network interface and the memory via the bus interface while performing protocol offload processing on the data packets.

Bus interface controller for cost-effective high performance graphics system with two or more graphics processing units

Abstract: A bus interface controller manages a set of serial data lanes. The bus interface controller supports operating a subset of the serial data lanes as a private bus.

Contactless means for supplying energy and data to bus users

Abstract: The device (1) has an energy transmission interface (3) for contactless energy supply of a bus subscriber, which is designed as an input/output device. A data transmission interface (4) is provided for contactless connection of the bus subscriber to a data bus. The energy transmission interface includes a primary coil for inductive transmission of electrical energy to a secondary coil, which is arranged in the bus subscriber, in such a manner that the function of the data transmission interface is satisfied. An independent claim is also included for a bus subscriber with a mounting unit for mounting the bus subscriber at the device for mechanical mounting of bus subscriber of a data bus.

Data communications system and method of data transmission

Abstract: A 1553 data communication system having a primary data bus, a redundant data bus and a non-1553 data communication overlay system is provided. The non-1553 data communication overlay system comprises a non-1553 bus controller terminal and a non-1553 remote terminal. Each non-1553 terminal includes a non-1553 transmitter block connected to the primary bus and the redundant bus for sending non-1553 signals, a non-1553 receiver block for receiving non-1553 signals and a non-1553 receive path selection block. The non-1553 receive path selection block selectively establishes a receive path between the primary data bus or the redundant data bus and the non-1553 receiver block according to predefined receive path selection criteria. A 1553 data communication method is also provided.

Design of a Map-Based Transit Itinerary Planner

Abstract: Geographic Information Systems (GIS) have provided a platform to present information over the Internet to potential users of public transportation. The advantage of using a GIS is that it allows the user to select an origin and destination on a map, easing the task of inputting information to the itinerary-planning process. In addition, the mapping features of GIS can provide a user-specific map showing the route(s) used in the itinerary, as well as local access, egress, and bus stop information. In this article, the design issues associated with the use of GIS in itinerary generation are discussed. Specific design principles are articulated, based on existing knowledge of requirements for the human-computer interface (HCI). In application of these principles, this article describes the implementation of an ArcIMS GIS-based itinerary planner for the Sun Tran bus network in Tucson, Arizona. This system provides users the option of selecting their origin or destination on the map, manually entering an address, or selecting a landmark from a pull-down menu. The routing algorithm then finds the optimum path, and the output is presented to the user both in text and on the map. This is unique from other itinerary planners because it provides an interactive point-and-click map feature that can be implemented using commercially available GIS software.

Method and device for synchronizing two bus systems and arrangement composed to two bus systems

Abstract: A device for synchronizing at least two bus systems, having a first communications module for a first bus system and a second communications module for a second bus system, wherein in the first communications module first trigger information is present by which a trigger signal is triggered in the first bus system, characterized in that the device is configured in such a manner that the first and second communications modules are connected to each other and the first trigger information is transmitted to the second communications module, and the second communications module is configured in such a manner that a time information value is determined from the first trigger information and that time information value is compared with a second time mark of the second bus system, a time difference being determined and the next reference message being triggered in the second bus system in dependence upon the second time mark and the time difference.

Weighted bus arbitration based on transfer direction and consumed bandwidth

Abstract: A bus arbitration algorithm precisely controls the relative bus channel bandwidth allocated to each master device by considering the direction of, and/or the bus channel bandwidth consumed by, a bus transaction. At least one weighting register is associated with each master device; in one embodiment, one weighting register per bus channel. The register is periodically loaded with a proportionate share of the available bus bandwidth. Upon being granted a bus transaction on a bus channel, the corresponding weighting register is decremented by an amount that reflects the bus channel bandwidth consumed by the transaction, measured in amount of data transferred or number of bus data transfer cycles required to complete the transaction. In the case of equal initial allocation of relative bandwidth share, master devices that consume bus channel bandwidth will have relatively low priority; master devices that do not consume bus channel bandwidth retain relatively high priority.

Multiple-valued logic buses for reducing bus energy in low-power systems

Abstract: The viability of bus interconnection models is explored, using the multiple-valued logic (MVL) paradigm to reduce the cost and energy consumption of off-chip and on-chip address, data and instruction buses within system-on-a-chip platforms. Data can be transferred over the buses using ternary, balanced ternary or quaternary number systems, rather than binary. This allows more compact bus design with a fewer number of bus lines, which can result in lower input/output pin cost for off-chip buses. Reducing the number of bus lines also allows us to increase the distance between the adjacent bus lines using the same silicon area. This further reduces interwire capacitance and may lead to significant on-chip bus energy reduction for low-power embedded systems. First, a combinatorial probabilistic view of digit transition patterns in binary and MVL number systems is provided. This is followed by an empirical study conducted by running various applications to measure bus switching activities as well as total bus energy consumption of real-world applications. It is observed that the number of bus transitions in a multiple-valued bus, particularly in a quaternary bus, is significantly less than the number of bus transitions in a binary bus. Our experimental results show that MVL bus models, replacing the binary equivalent, can be viable interconnection structures and are able to provide up to 29, 29 and 30% reduction in energy consumption for off-chip address, data and instruction buses, respectively. These savings are 55, 53 and 62% for on-chip quaternary address, data and instruction buses, respectively using 0.25 /spl mu/m technology.

Extending secure digital input output capability on a controller bus

Abstract: Embodiments of techniques for simultaneously connecting a plurality of expansion cards to a single bus of a host controller are described.

Experimental multiuser quantum key distribution network using a wavelength-addressed bus architecture

Abstract: A six-user quantum key distribution network implemented on a bus topology is experimentally demonstrated. The network employs the BB84 protocol to transmit cryptographic keys encoded unto the phase states of highly attenuated laser light to distances of up to 31 km in a standard telecommunication-grade fiber. Each user on the network is assigned a unique wavelength for communication with the network server at a time. The measured quantum bit error rate and sifted key rate compare favorably with theoretical results

Method to embed protocol for system management bus implementation

Abstract: A method of adapting the System Management Bus protocol to increase the number of peripheral components accessible to a control processor, the method including embedding a component address having a length of up to seven bits in a System Management Bus Block Write and completing a system transaction with the System Management Bus Block Write and a second data packet so that data is sent between the control processor and the peripheral component having the component address.

Packet capture agent for use in field assets employing shared bus architecture

Abstract: A field asset suitable for use in a machine to machine environment includes a machine controller configured to function as a master of a shared bus (e.g. an MDB bus) and one or more slave peripheral devices connected to the bus. The field asset includes a snoop agent to capture packets transmitted on the shared bus. The snoop agent may be implemented as a microcontroller coupled to the MDB bus via a UART and isolation circuitry and controlled by appropriate packet capture firmware. The microcontroller may capture and buffer captured data and send the buffered data to a snoop application module. The application module may be implemented as part of an extended function adapter including an embedded processor in communication with the microcontroller.

Communication apparatus implementing time domain isolation with restricted bus access

Abstract: A communication apparatus includes a radio frequency circuit that operates on a radio frequency signal and a digital processing circuit coupled to the radio frequency circuit. The digital processing circuit includes a plurality of bus masters coupled to a shared bus. A bus arbiter is provided for arbitrating between requests to access the bus by a first bus master and one or more other bus masters. Accesses by the one or more other bus masters to the bus are restricted in response to a signal indicative of a change in a mode of operation of the RF circuit. In one particular implementation, a communication apparatus employs time domain isolation wherein the digital processing circuit may be placed in a shutdown mode when the radio frequency circuit is active.

Computer bus power consuming device

Abstract: A power-using device for drawing power over a communication and power bus is provided. The power-using device is adapted to draw only power from the communication and power bus, the bus being connected to a power supply and host computer. The power-using device is further capable of communicating with the bus via a host bus adapter through a communication link not comprised by the bus. The host bus adapter is capable of receiving power and communication from the bus.

A low-cost memory remapping scheme for address bus protection

Abstract: The address sequence on the processor-memory bus can reveal abundant information about the control flow of a program. This can lead to critical information leakage such as encryption keys or proprietary algorithms. Addresses can be observed by attaching a hardware device on the bus that passively monitors the bus transaction. Such side-channel attacks should be given rising attention especially in a distributed computing environment, where remote servers running sensitive programs are not within the physical control of the client. Two previously proposed hardware techniques tackled this problem through randomizing address patterns on the bus. One proposal permutes a set of contiguous memory blocks under certain conditions, while the other approach randomly swaps two blocks when necessary. In this paper, we present an anatomy of these attempts and show that they impose great pressure on both the memory and the disk. This leaves them less scalable in high-performance systems where the bandwidth of the bus and memory are critical resources. We propose a lightweight solution to alleviating the pressure without compromising the security strength. The results show that our technique can reduce the memory traffic by a factor of 10 compared with the prior scheme, while keeping almost the same page fault rate as a baseline system with no security protection.

High speed bus protocol with programmable scheduler

Abstract: A method of adapting the frequency of a protocol in a communication system is provided. The method includes changing a bus cycle used by communication nodes in a communication system based on cycle interval instructions.

Method for changing ownership of a bus between master/slave devices

Abstract: A system may comprise multiple master/slave devices coupled to a common bus, where one of the devices may operate as the current master device and the other devices may operate as current slave devices. Current slave devices may embed bus ownership request information within response packets transmitted in response to standard bus operations, such as reads and writes, issued by the current master device. When the current master device is idle, its bus interface may continually poll the current slave devices at regular intervals, according to a specified protocol, to ascertain whether any of them are requesting bus ownership. A response to a request for bus ownership received by the current master device may be configured according to desired system functionality. In one system, ownership may always be transferred to the requesting device. In other systems, the current master device may transmit a subsequent standard bus operation request packet, or a unique response packet, either comprising embedded information indicating whether ownership of the bus has been granted.

Optimizing power usage by factoring processor architecutral events to pmu

Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.

Apparatus and method for enabling a multi-processor environment on a bus

Abstract: The present invention provides a technique for enabling multiple devices to be interfaced together over a bus that requires dynamic impedance controls. In one embodiment, an apparatus is provided for enabling a multi-device environment on a bus, where the bus requires active termination impedance control. The apparatus includes a first node and multi-processor logic. The first node receives an indication that a corresponding device is at a physical end of the bus. The multi-processor logic is coupled to the first node. The multi-processor logic controls how a second node is driven according to the indication, where the second node is coupled to the bus.

Latency-Guided On-Chip Bus-Network Design

Abstract: Deep submicrometer technology scaling has two major ramifications on the design process. First, reduced feature size significantly increases wire delay, thus resulting in critical paths being dominated by global interconnect rather than gate delays. Second, an ultrahigh level of integration mandates design of systems-on-chip that encompass numerous design blocks of decreased functional granularity and increased communication demands. The convergence of these two factors emphasizes the importance of the on-chip bus network as one of the crucial high-performance enablers for future systems-on-chip. An on-chip bus-network design methodology and corresponding set of tools which, for the first time, close the synthesis loop between system and physical design have been developed. The approach has three components: a communication profiler, a bus-network designer, and a fast approximate floorplanner. The communication profiler collects run-time information about the traffic between system cores. The bus-network design component optimizes the bus-network structure by coordinating information from the other two components. The floorplanner aims at creating a feasible floorplan; it also sends feedback about the most constrained parts of the network. The effectiveness of our bus-network design approach on a number of multicore designs is demonstrated

Method and arrangement for the automatic configuration of a master-slave field bus system

Abstract: The invention relates to a field bus system (16), especially a LIN bus system, comprising a master (14) and at least one bus subscriber (15). In order to carry out an automatic configuration of the bus system, the master (14) stores the current configuration of the field bus system (16) as the known configuration, and carries out the following steps after restarting the bus system: a standard address is allocated as a subscriber address to the at least one bus subscriber (15); it is checked whether the at least one bus subscriber (15) belongs to the known configuration and, if this is the case, a unique subscriber address is allocated thereto (15); it is then checked whether the at least one bus subscriber (15) still has the standard address and, if this is the case, the at least one bus subscriber is identified and a unique subscriber address is allocated thereto.

Contribution to the design of the athletes bus network during the Athens 2004 Olympic Games

Abstract: This paper describes important aspects of the design of the Athletes transportation system for the Athens 2004 Olympic Games. The unique characteristics of this network include the close dependence of the vehicle schedules on the competition and training program, the requirement for 100% service reliability, as well as the requirement for full system monitoring and control. In this paper we present methods for the development of service specifications, estimation of the bus fleet size, the design of the network’s organization and management system, and corresponding critical implementation issues. All these issues are relevant to the design and management of bus transport systems for large events.