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Showing papers on "Bus network published in 2008"


Journal ArticleDOI
TL;DR: This analysis suggests that the larger sample size available from electronic farecard records enables more comprehensive, detailed ODMs than those generated from traditional household survey data.
Abstract: This paper outlines the process used to create an origin-destination matrix (ODM) in Sao Paulo, Brazil, with data available from automated data collection (ADC) systems. Prior work to develop ODMs using ADC systems is reviewed; however, the Sao Paulo case differs substantially from these. The approach used in this paper addresses a more complex bus network than has been approached before, uses a platform for integrating more data than were available in previous applications, and applies raw global positioning system-coordinate data to determine the location of buses for assigning an origin zone. Previously documented destination-inference techniques are used to assign destinations to each trip. Overall, the ODM development process uses three data sources: bus stops, automatic vehicle location data, and automated fare collection data. The results of the electronically generated ODM are analyzed and compared with results from prior household surveys. This analysis suggests that the larger sample size availa...

96 citations


Patent
29 Jan 2008
TL;DR: In this paper, a method and system monitor a communications network, e.g., a controller area network (CAN), and more specifically, an in-vehicle communications network by maintaining a count of each type of error code and a histogram of all network messages seen by each of the controllers during a measurement period.
Abstract: A method and system monitor a communications network, e.g., a controller area network (CAN), and more specifically, an in-vehicle communications network, by maintaining a count of each type of error code and a histogram of all network messages seen by each of the controllers during a measurement period; and by determining a bus health index of the communication bus based upon a percentage of a given type of error to the total count of all errors during a measurement period. An individual controller or controller area network bus segment can be indicated as having a communications problem as a result of the health index.

76 citations


Patent
18 Mar 2008
TL;DR: In this paper, the authors propose a broadband multi-drop local network, interface and method for multimedia access, which includes a wired bus coupleable directly to an external data network terminal and configured for carrying broadband packetized data traffic over a frequency spectrum uninterrupted by other defined data channels or services.
Abstract: A broadband multi-drop local network, interface and method for multimedia access. A local network architecture include a wired bus coupleable directly to an external data network terminal and configured for carrying broadband packetized data traffic over a frequency spectrum uninterrupted by other defined data channels or services; and one or a plurality of network transceivers operable individually for coupling an addressable network device processing a defined class of information to the bus wherein each network appliance is configured for and further operable for providing communication interfacing of the class of information of each addressable network appliance with the packetized IP data traffic on the wired bus.

70 citations


Journal ArticleDOI
TL;DR: The results show that considering the loss in a network with different voltage levels decreases the operational costs considerably, and the network satisfies the requirement of delivering electric power more safely and reliably to load centers.

66 citations


Proceedings ArticleDOI
15 Apr 2008
TL;DR: This paper presents BLER, a routing algorithm that achieves effective routing in a buses environment that performs routing at bus line level instead of bus level; it uses specific bus lines information to achieve good performances.
Abstract: A disruption-tolerant network (DTN) attempts to route packets between nodes that are temporarily connected. Difficulty in such networks is that nodes have no information about the network status and contact opportunities. The situation is different in public bus networks because the movement of buses exhibits some regularity so that routing in a deterministic way is possible. Many algorithms use a contacts oracle that provides the exact meeting times and durations between all nodes. However, in a real vehicular environment, an oracle is not always accurate, and deterministic routing gives poor results. In this paper, we present BLER, a routing algorithm that achieves effective routing in a buses environment. BLER, compared to other algorithms, performs routing at bus line level instead of bus level; it uses specific bus lines information to achieve good performances. We evaluate BLER on real traces of the bus network of Shanghai, and compare it to other routing algorithms. Performances provide good results for this kind of DTNs.

60 citations


Patent
Michael G. Love1
04 Feb 2008
TL;DR: In this article, an on-chip bus architecture involving a collector node and at least one device node is described, where the collector node is capable of conducting multiple outstanding transactions with a plurality of onchip devices over the onchip bus.
Abstract: This disclosure involves an on-chip bus architecture involving an on-chip bus that includes a collector node and at least one device node. Each device node is in communication with an on-chip device. The collector node is capable of conducting multiple outstanding transactions with a plurality of on-chip devices over the on-chip bus wherein each on-chip device transmits all of its data signals across the on-chip bus in the form of packets. The on-chip bus includes at least one bus register, and each of the multiple on-chip devices includes at least one device register. The on-chip bus can provide top level register to register communications between the device register and the bus register. In one version, the on-chip bus is a distributed packet on-chip (DPO) bus.

56 citations


Patent
07 Dec 2008
TL;DR: In this paper, a system that includes multiple modules of an integrated circuit, a network on chip that is coupled to the multiple modules, and a bus, coupled in parallel to the NOC, is described.
Abstract: A system that includes multiple modules of an integrated circuit; a network on chip that is coupled to the multiple modules; a bus, coupled in parallel to the network on chip to the multiple modules; wherein a latency of the bus is lower and more predictable than an average latency of the network of chip.

47 citations


Patent
22 Dec 2008
TL;DR: In this paper, a hierarchical bus structure is proposed for voice processing applications, in which clusters of processors are arranged and interconnected within a hierarchy to facilitate processor communications via shared memories, and a memory access protocol in which the address and data portions of shared-memory access operations are performed as separate bus transactions that are separated in time.
Abstract: A hierarchical bus structure is disclosed in which clusters of processors are arranged and interconnected within a hierarchy to facilitate processor communications via shared memories. The bus structure is well suited for voice processing applications in which clusters of embedded processors process voice streams in parallel, although the architecture is not so limited. Also disclosed is a memory access protocol in which the address and data portions of shared-memory access operations are performed as separate bus transactions that are separated in time, such that multiple concurrent memory access operations from different processors may be interleaved over a shared bus.

40 citations


Journal ArticleDOI
TL;DR: Three models of minimal cost flow problem in fuzzy nature, after defining a total order on LR type fuzzy numbers, are studied and “nominal flow” is introduced which provides an efficient scheme for finding fuzzy flow.

39 citations


Patent
27 Mar 2008
TL;DR: A processor local bus bridge for a processor block ASIC core for embedding in an IC is described in this paper, where a crossbar switch coupled to the master and slave processor local interfaces is used for bridging.
Abstract: A processor local bus bridge for a processor block ASIC core for embedding in an IC is described. A core logic-to-core logic bridge includes a slave processor local bus interface, a crossbar switch coupled to the slave processor local bus interface and a master processor local bus interface coupled to the crossbar switch. The slave processor local bus interface and the master processor local bus interface are coupled to one another via the crossbar switch for bidirectional communication between a first and a second portion of core logic. The bridge provides rate adaptation for bridging for use of a frequency of operation associated with the crossbar switch which has substantially greater frequencies of operation than those associated with the core logic sides of the master and slave processor local bus interfaces.

36 citations


Patent
22 Jan 2008
TL;DR: In this paper, the authors propose a virtual bus model that simulates behavior for a bus master and slave device, such that the model accurately simulates the timing and behavior of the transfer of data from master to slave, and, from slave to master devices.
Abstract: Systems and methods for modeling a bus for a system design are provided. In an embodiment, the method operates by accepting a virtual bus model, wherein the model simulates behavior for a bus master and slave device, such that the model accurately simulates the timing and behavior of the transfer of data from master to slave, and, from slave to master devices. The method routes a transaction issued by the master device to the slave device. The transaction has storage for transaction data, or a pointer to transaction data, to be transferred through the transaction. The transaction data is transferred in one or more data payloads and the sender of data sets the length of data payloads to be returned. The data payloads are sent from the sender of data to the receiver of data and may contain one or more bus data beats. This method accurately models the bus timing and behavior of the delivery of one or more data beats as one data payload.

Proceedings ArticleDOI
07 Feb 2008
TL;DR: The classification of topology control of emerging wireless sensor network field is examined, based on different Network models, graph models and node groupings, allowing network designers to choose the protocol architecture that best matches the goals of their application.
Abstract: Wireless sensor network is a densely deployed resource stress network where each small chunk of resource adds the high value to over all network functionality. Topology control is a technique through which network controls it's dense deployment for efficient resource utilization. This article examines the classification of topology control of emerging wireless sensor network field, based on different Network models, graph models and node groupings. Further article covers the effect of mobility on topology control and various topology control measurement parameters. This article will aid in defining appropriate topology control mechanism, allowing network designers to choose the protocol architecture that best matches the goals of their application. In addition, this article will enable new sensor network topology control method to be defined for use in further research in this area.

Patent
Toshio Otani1
07 Apr 2008
TL;DR: In this article, the authors proposed a system that assigns a world wide name and a network address to a source host bus adaptor associated with one SCSI node and then relocate the network address associated with the source host adaptor to another SCSI nodes.
Abstract: In one implementation, a system includes multiple SCSI nodes configured to perform a SCSI target function. Each of the multiple SCSI nodes includes a host bus adaptor configured to connect the SCSI node with a Fiber Channel fabric. The host bus adaptor being assigned a world wide name and a network address. The system further includes a host configured to perform a SCSI initiator function. The world wide name assigned to a source host bus adaptor associated with one SCSI node is relocated to a target host bus adaptor associated with another SCSI node. After that, the network address associated with the source host bus adaptor is relocated to the target host bus adaptor. In one implementation, the system determines whether or not a network address assigned to a source host bus adaptor associated with one of the multiple SCSI nodes is shared with at least one other service. If so, the system determined whether the shared network address can be relocated to a target host bus adaptor associated with another one of the multiple of SCSI nodes. If the latter determination is in affirmative, the world wide name and network address are relocated.

Patent
31 Jul 2008
TL;DR: In this article, a peer-to-peer special purpose processor architecture and method is described, where a plurality of special purpose processors coupled to a central processing unit via a host bridge bus, a direct bus directly coupling each of the plurality of SPMs to at least one other SPM, and a memory controller coupled to the plurality, where the memory controller determines whether to transmit data via the host bus or the direct bus.
Abstract: A peer-to-peer special purpose processor architecture and method is described. Embodiments include a plurality of special purpose processors coupled to a central processing unit via a host bridge bus, a direct bus directly coupling each of the plurality of special purpose processors to at least one other of the plurality of special purpose processors and a memory controller coupled to the plurality of special purpose processors, wherein the at least one memory controller determines whether to transmit data via the host bus or the direct bus, and whether to receive data via the host bus or the direct bus.

Proceedings ArticleDOI
26 Aug 2008
TL;DR: An optical data bus for computer interconnections that has two sets of optical waveguides that are used to interconnect different modules attached to the bus, with an aggregate bandwidth of over 25 GB/s.
Abstract: Buses have historically provided a flexible communications structure in computer systems. However, signal integrity constraints of high-speed electronics have made multi-drop electrical busses infeasible. Instead, we propose an optical data bus for computer interconnections. It has two sets of optical waveguides, one as a fan-out and the other as a fan-in, that are used to interconnect different modules attached to the bus. A master module transmits optical signals which are received by all the slave modules attached to the bus. Each slave module in turn sends data back on the bus to the master module. Arrays of lasers, photodetectors, waveguides, microlenses, beamsplitters and Tx/Rx integrated circuits are used to realize the optical data bus. With 1 mW of laser power, we are able to interconnect 8 different modules at 10 Gb/s per channel. An aggregate bandwidth of over 25 GB/s is achievable with 10 bit wide signaling paths.

Proceedings ArticleDOI
21 Apr 2008
TL;DR: RS-232 with the excellences of working in ISM (industry, science, medicine) domains and having built-in UART (asynchronism serial receival) interface, combined with CAN, could realize data communication between PC serial interface and CAN bus fleetly and exactly.
Abstract: With the plentiful application of various electronic equipments and control devices which used in industry, the communication networks based on field bus are produced. Connection between CAN bus and normal bus RS-232 which is used in existing serial communication, could realize to construct network with multidrop and long-distance communication. Method of conversion between RS-232 and CAN bus is discussed and a communication convertor with new design and debug is introduced in the paper. In order to conquer the illogicalities or conflictions brought from bus configuration and communication protocol of various controller, it is chosen unattached bus controller SJA1000 and singlechip AT89C51 to constitute CAN bus brainpower node in the convertor; made use of MAX232 to complete the level conversion from 232 to micro controller interface card TTL; provided differential sending capability of bus and differential incepting capability of CAN controller. RS-232 with the excellences of working in ISM (industry, science, medicine) domains and having built-in UART (asynchronism serial receival) interface, combined with CAN, could realize data communication between PC serial interface and CAN bus fleetly and exactly. It was examined through debug that there are some advantages of long direct communication distances, high communication velocity, simple configuration, low cost with the design. And it could replace the CAN interface card with high price in current market for reasons of simple configuration and low-cost.

Proceedings ArticleDOI
20 Dec 2008
TL;DR: In this paper, a bus bridge is implemented to bridge CPU and dual bus and the result has proved that the architecture based on single CPU andDual bus is reasonable and effective.
Abstract: Single CPU dual bus architecture is a new kind of architecture aimed at reducing the security vulnerability of Von Neumann architecture, and it has been proved theoretically reasonable. In this paper, a bus bridge is implemented to bridge CPU and dual bus. The experiment is done and the result has proved that the architecture based on single CPU and dual bus is reasonable and effective.

Patent
Rajaram B. Krishnamurthy1
29 Jan 2008
TL;DR: In this paper, a method and system for migrating network resources to improve network utilization, for use in a multi-node network wherein nodes of the network share network resources, is disclosed for MNOs.
Abstract: A method and system are disclosed for migrating network resources to improve network utilization, for use in a multi-node network wherein nodes of the network share network resources. The method comprises the steps of identifying a group of nodes that share one of the network resources, and identifying one of the nodes satisfying a specified condition based on at least one defined access latency metric. The shared resource is moved to the identified one of the nodes to reduce overall access latency to access the shared resource by said group of nodes. One embodiment of the invention provides a method and system to synchronize tasks in a distributed computation using network attached devices (NADs). A second embodiment of the invention provides a method and system to reduce lock latency and network traffic by migrating lock managers to coupling facility locations closest to nodes seeking resource access.

Patent
02 Dec 2008
TL;DR: In this paper, the authors present a method and apparatus for a control bus for connection of electronic devices, which includes coupling a transmitting device to a receiving device, including connecting a controller bus between the transmitting device and the receiving device.
Abstract: A method and apparatus for a control bus for connection of electronic devices. An embodiment of a method includes coupling a transmitting device to a receiving device, including connecting a control bus between the transmitting device and the receiving device, with the control bus being a bi-directional, single-line bus. The method further includes obtaining control of the control bus for either the transmitting device or the receiving device, with the device obtaining control becoming an initiator and the other device becoming a follower. One or more control signals are converted to one or more data packets, with each of the one or more control signals representing one of multiple different types of control signals. The generated data packets are transmitted from the initiator to the follower via the control bus.

Patent
06 Jun 2008
TL;DR: In this article, the storage system architecture allows the microprocessor to simultaneously broadcast a command to the media controllers, which have a capability to substantially simultaneously begin exchanging data with the storage media in response to the command.
Abstract: A storage system controller (302) includes a plurality of media controllers (301), a local microprocessor (306), and a host interface logic (310), operably coupled by a multi-drop bus. The multi-drop bus includes a control bus (324), a payload data bus (320), a real-time ready-status (data ready) signaling bus (322) and a general microprocessor bus (330). Each media controller has a storage media (311) operably coupled thereto. Each media controller includes a parameter storage (404), a media interface circuit (406), a control data state machine (408), a command sequencer state machine (410), a media-side multi-mode transfer state machine (412), a dual-port memory (402), a memory controller (420), and a host-side transfer state machine (430). The host interface logic and the media controllers are implemented in one or more Field Programmable Gate Arrays. The storage system architecture allows the microprocessor to simultaneously broadcast a command to the media controllers, which have a capability to substantially simultaneously begin exchanging data with the storage media in response to the command. The storage system has provision for Redundant Array of Independent Disks, method 0, operation.

Proceedings ArticleDOI
06 Oct 2008
TL;DR: This new architecture is aimed to build a kind of low-cost intrusion-free network computer and reduce vulnerability of Neumann model, comprised of one CPU and two physically isolated system buses, secure and non-secure.
Abstract: Internet is facing a serious problem: open and security. Private data, such as credit card information, login account and password, and etc., is easily theft by hackers. In this paper, we propose a new secure architecture of network computer (SANC). This new architecture is aimed to build a kind of low-cost intrusion-free network computer and reduce vulnerability of Neumann model. It is comprised of one CPU and two physically isolated system buses, secure and non-secure. Only non-secure bus has Internet interfaces. Devices, storing private data, can only be accessed through secure bus. Internet related applications, only running on the non-secure bus, have no opportunity to access resources on the secure bus. Besides, only one CPU can efficiently control the cost. To control the connection between CPU and two system buses, and ensure only one bus can be connected to CPU at the same time, a bus bridge (BB) is designed.

Book ChapterDOI
01 Jan 2008
TL;DR: This chapter presents the research on techniques for efficient bus-based communication architecture synthesis, and discusses physical implementation aware synthesis and memory–communication architecture cosynthesis.
Abstract: Publisher Summary The design of on-chip communication architectures is becoming more challenging as the number of components integrated into a single embedded multiprocessor system-on-chip (MPSoC) increases due to greater market demands for convergence devices. The increasing number of components in systems translates into more intercomponent communication that must be handled by the on-chip communication infrastructure. This chapter presents the research on techniques for efficient bus-based communication architecture synthesis. Some of these techniques focus on either bus topology design, or on the synthesis of bus protocol parameters, such as arbitration schemes, bus widths, and clock frequencies for a fixed bus topology. However, the communication architecture design space is a combination of the topology and protocol parameter spaces, and there have been approaches that also comprehensively synthesize both topology and protocol parameter values, for different design constraints. The chapter also discusses physical implementation aware synthesis and memory–communication architecture cosynthesis.

Patent
26 Sep 2008
TL;DR: In this article, a means for reliable inter-processor communication in a multi-processor system is described, where a speciallyconfigured serial bus is used as a general-purpose data link between a first processor and a second processor.
Abstract: A means for reliable inter-processor communication in a multi-processor system is described. In accordance with one aspect, a specially-configured serial bus is used as a general-purpose data link between a first processor and a second processor. The serial bus may be an Inter-IC Sound (I2S) bus. In accordance with another aspect, a network interface residing on a second processor is made available to a first processor via a data link established over an I2S bus. This allows the second processor to be used as a proxy and to support remote configuration and network address traversal.

Proceedings ArticleDOI
23 Sep 2008
TL;DR: A dedicated hardware used to allow an external accelerator to access the system memory independently from the main microprocessor is presented, able to exchange data with the memory in a DMA-like fashion, to generate properly memory addresses in order to access it in an efficient way.
Abstract: A very common problem which affects the performance of bus-based computing systems arises from the fact that the bus is a common resource which needs to be shared between a number of master devices. The common resource contention forces to stall temporarily the execution of one or more of the bus masters, slowing down the execution. Moreover, the width of the bus is usually relatively small, forcing the bus master to perform several bus cycles in order to transfer a data block from the main memory to a peripheral (or to a processing element), and the other way around. The combination of these factors leads to problems and inefficiencies which designers need to solve. In this paper we present a dedicated hardware used to allow an external accelerator to access the system memory independently from the main microprocessor. The proposed device is able to exchange data with the memory in a DMA-like fashion, to generate properly memory addresses in order to access it in an efficient way. Results show that using such a solution it is possible to reach a considerable speed-up in the execution of a given algorithm.

Patent
24 Sep 2008
TL;DR: In this article, the authors present an approach to improve the efficiency of transfer of control information, graphic data, and the like for drawing and display control in a graphic data processor.
Abstract: An object of the present invention is to improve efficiency of transfer of control information, graphic data, and the like for drawing and display control in a graphic data processor. A graphic data processor includes: a CPU; a first bus coupled to the CPU; a DMAC for controlling a data transfer using the first bus; a bus bridge circuit for transmitting/receiving data to/from the first bus; a three-dimensional graphics module for receiving a command from the CPU via the first bus and performing a three-dimensional graphic process; a second bus coupled to the bus bridge circuit and a plurality of first circuit modules; a third bus coupled to the bus bridge circuit and second circuit modules; and a memory interface circuit coupled to the first and second buses and the three-dimensional graphic module and connectable to an external memory, wherein the bus bridge circuit can control a direct memory access transfer between an external circuit and the second bus.

Patent
01 Jul 2008
TL;DR: In this paper, a communication interface device, system, method, and design structure for enhancing bus efficiency and utilization in a memory system is presented, which includes a first bus interface to communicate on a high-speed bus, a second bus interface for communicating on a lower speed bus, and clock ratio logic configurable to support multiple clock ratios between the high speed bus and the lower speed buses.
Abstract: A communication interface device, system, method, and design structure for enhancing bus efficiency and utilization in a memory system. The communication interface device includes a first bus interface to communicate on a high-speed bus, a second bus interface to communicate on a lower-speed bus, and clock ratio logic configurable to support multiple clock ratios between the high-speed bus and the lower-speed bus. The clock ratio logic reduces a high-speed clock frequency received at the first bus interface and outputs a reduced ratio of the high-speed clock frequency on the lower-speed bus via the second bus interface supporting variable frame sizes.

Patent
14 Jul 2008
TL;DR: In this article, a load center includes an enclosure, a first power input, a second power input and an output, and a transfer switch having a first input electrically connected to the first bus, an output connected to both the first and second inputs to its output.
Abstract: A load center includes an enclosure, a first power input, a second power input, a first circuit breaker having a line terminal electrically connected to the first power input and a load terminal, a first bus electrically connected to the load terminal, a number of independent second circuit breakers powered from the first bus, a second bus, a number of independent third circuit breakers powered from the second bus, and a transfer switch having a first input electrically connected to the first bus, a second input electrically connected to the second power input, and an output electrically connected to the second bus. The transfer switch selectively electrically connects one of its first and second inputs to its output. The first bus and the second circuit breakers power only a number of non-critical loads. The second bus and the third circuit breakers power only a number of critical loads.

Patent
10 Jan 2008
TL;DR: In this article, the authors present a bus-assisted actuator system, where the bus subscribers are formed as actuators, and each actuator has a controlling and programming unit that realizes bus communication as the functionality of the actuator application.
Abstract: The system has a configuration pushbutton (27) for starting of a bus configuration of bus subscribers that are connected by an application bus, where the bus subscribers are formed as actuators. Each actuator has a controlling and programming unit that realizes bus communication as the functionality of the actuator application. Each actuator is registered by a gateway (20) of a code number. Each actuator loops a primary voltage (14) and an auxiliary voltage (16) to the successive actuator. Each actuator has a display for its operation condition. An independent claim is also included for a method for controlling a bus-linked device.

Patent
Detlef Kuschke1
06 Oct 2008
TL;DR: In this article, the authors propose a control device that is constructed to communicate via the communications network in response to a selection signal according to a first communications bus sub-system or according to the second communications sub-carrier.
Abstract: The invention relates to a communications entity for communications via a bus-oriented communications network with a control device ( 101 ) that is constructed to communicate via the communications network in response to a selection signal according to a first communications bus sub-system or according to a second communications bus sub-system, and a selection device ( 103 ) for generating the selection signal as a function of an operating mode of the communications entity, in order to select the first communications bus sub-system or the second communications bus sub-system

Patent
16 Dec 2008
TL;DR: In this article, a modular data transmission system with several modules or bus nodes that can be arranged adjacent to one another in a row is described. But the authors do not specify how to construct such a system.
Abstract: The invention pertains to a modular data transmission system with several modules or bus nodes that can be arranged adjacent to one another in a row. The data transmission system comprises a first bus node that features a first transmitter for the wireless transmission of data and an electrical connector, as well as a second bus node that features a first receiver for the wireless reception of data and an electrical connector. Both bus nodes are detachably fixed on a mounting rail such that they are arranged adjacent to one another in a row. The first and second bus nodes are respectively detachably connected to a bus receptacle, wherein each bus receptacle features an electrical mating connector that is coupled to the electrical connector of the respective bus node in the connected state in order to transmit energy, as well as a positioning device for positioning the respective bus node.