Showing papers on "Bus network published in 2010"

Closed-grid bus architecture for wafer interconnect structure

Abstract: An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can concurrently communicate with all of the I/O pads. The interconnect structure includes a circuit board implementing an array of bus nodes, each corresponding to a separate one of the I/O pads. The circuit board includes at least two layers. Traces mounted on a first layer form a set of first daisy-chain buses, each linking all bus nodes of a separate row of the bus node array. Traces mounted on a second circuit board layer form a set of second daisy-chain buses, each linking all bus nodes of a separate column of the bus node array. Vias and other circuit board interconnect ends of the first and second daisy-chain buses so that they form the closed-grid bus. Each bus node is connected though a separate isolation resistor to a separate contact pad mounted on a surface of the circuit board. A set of spring contacts or probes link each contact pad to a separate one of the I/O pads on the wafer.

The Concept of Betweenness in the Analysis of Power Grid Vulnerability

Abstract: Vulnerability analysis in power systems is a key issue in modern society and many efforts have contributed to the analysis. Recently, complex network metrics applied to assess the topological vulnerability of networked systems have been used in power systems, such as betweenness metric, since transmission of power systems is in basis of a network structure. However, a pure topological approach fails to capture the specificity of power systems. This paper redefines, starting from the concept of complex networks, an electrical betweenness metric which considers several of specific features of power systems such as power transfer distribution and line flow limits. The electrical betweenness is compared with the conventional betweenness in IEEE-300 bus network according to the un-served energy after network is attacked. The results show that the tested network is more vulnerable when the components of the network are attacked according to their criticalities ranked by electrical betweenness.

Design method of CAN BUS network communication structure for electric vehicle

Abstract: According to the communication structure of CAN BUS network on EV, this paper works out a SAE J1939 application layer protocol meet the system functional requirements, and designs the software and hardware for the system. First, design the CAN BUS work nod for EV, including the master node, the light node, air conditioning node, doors and instrument node, etc, and the draw the CAN BUS topology diagram. Meanwhile, according to the concrete situation of EV, work out an application layer protocol that consistent with the SAE J1939 protocol, and the information allocation table and message structure chart of CAN BUS network node is also presented. Secondly, design the hardware and software for the CAN BUS communication network. Hardware interface circuit mainly consist of CAN communication controller SJA1000, high-speed opt coupler 6N137 and CAN BUS driver 82C250, and design schematic circuit diagram for CAN bus system hardware. The software designs for CAN BUS network are mainly the design of CAN BUS data communication and exchange between nodes, and communication processing for switch-signal, analog signal. The design of software communication module includes CAN initialization unit, message sending unit, message receiving unit and the interrupt service unit. Finally, the CAN BUS network communication system the paper designed is applied to the new energy bus produced by CENS Energy-Tech Co., Ltd. which is dedicated in the Shanghai World Expo. From the battery voltage data collected when EV are running, we can see that the system is accurate, stable without number lost, frame dropping and transfer error in data communication. The design has practical value promoting the application of new energy vehicles.

Using intelligent agents for Transportation Regulation Support System design

Abstract: This paper presents an agent-based approach used to design a Transportation Regulation Support System (TRSS), that reports the network activity in real-time and thus assists the bus network regulators. The objective is to combine the functionalities of the existing information system with the functionalities of a decision support system in order to propose a generic model of a traffic regulation support system. Unlike the other approaches that only deal with a specific task, the original feature of our generic model is that it proposes a global approach to the regulation function under normal conditions (network monitoring, dynamic timetable management) and under disrupted conditions (disturbance assessment and action planning of feasible solutions). Following the introduction, the second section presents the notions of the domain and highlights the main regulation problems. The third section details and motivates our choice of the components of the generic model. Based on our generic model, in the fourth section, we present a TRSS prototype called SATIR (Systeme Automatique de Traitement des Incidents en Reseau - Automatic System for Network Incident Processing) that we have developed. SATIR has been tested on the Brussels transportation network (STIB). The results are presented in the fifth section. Lastly, we show how using the multi-agent paradigm opens perspectives regarding the development of new functionalities to improve the management of a bus network.

Single wire bus system

Abstract: There is provided a single wire bus architecture comprising a single wire bus; a master device coupled to the single wire bus; at least one slave device coupled to the single wire bus; a communication protocol implemented over the single wire bus and employed by the master device and the at least one slave device; wherein when one of the at least one slave devices wishes to communicate with the master device, the one of the at least one slave devices discharges the clock signal during a tri-state stage of the clock signal; and wherein the single wire bus transmits a clock signal, power and data between the master device and the one of the at least one slave device in communication with the master device.

Electrical power distribution

Abstract: The present invention relates generally to electrical power distribution, for example, in aircraft. More particularly, according to a first aspect, the present invention relates to a power supply system for power distribution to one or more loads in a safety-critical power supply network. The power supply system comprises at least one power source, a power bus and a distributed control system. The distributed control system comprises a central controller operably coupled to at least one bus module through a data bus. Bus modules include bus controllers that are operable to connect respective power sources to the power bus.

Network interface device with flow-oriented bus interface

Abstract: A network interface device includes a bus interface that communicates over a bus with a host processor and memory, and a network interface that sends and receive data packets carrying data over a packet network. A protocol processor conveys the data between the network interface and the memory via the bus interface while performing protocol offload processing on the data packets in accordance with multiple different application flows. The bus interface queues the data for transmission over the bus in a plurality of queues that are respectively assigned to the different application flows, and transmits the data over the bus according to the queues.

Data Sensor Coordination Using Time Synchronization in a Multi-Bus Controller Area Network System

Abstract: A method is provided for synchronizing time in an unsynchronized vehicle controller area network system. A master control unit receives a global time from a time synchronization source. The master control unit estimates a respective time delay in transmitting messages by electronic control units on each controller area network bus. The time delay is a difference between a time when a message is generated by a respective electronic control unit for transmission on a respective controller area network bus and a time when the message is transmitted on the respective controller area network bus. The global time is adjusted for each respective controller area network bus based on the estimated time delays associated with each respective controller area network bus. Global time messages from the master control unit are transmitted to each electronic control unit that include the adjusted global times for an associated controller area network bus.

Processor bus bridge security feature for network processors or the like

Abstract: Described embodiments provide a system having a bridge for communicating information between two processor buses. The bridge receives a command from a first bus, the command having an identification field and an address field. As the command is entered into a buffer in the bridge, the address field is checked against one or more addresses. If there is a match, then control bits are checked to see if the command will be allowed or not depending on the identification field value. If the command is not transferred to the second bus, a flag is set in the buffer, and an error message is returned to the first bus, and an interrupt may be generated. The control bits allow commands access to specific addresses on the second bus or deny the access depending on the command identification field. Bit-wise masking provides a range of values for identification and address field matching.

The Wireless Control Network: Synthesis and robustness

Abstract: We consider the problem of stabilizing a plant with a network of resource constrained wireless nodes. Traditional networked control schemes are designed with one of the nodes in the network acting as a dedicated controller, while the other nodes simply route information to and from the controller and the plant. We introduce the concept of a Wireless Control Network (WCN) where the entire network itself acts as the controller. Specifically, at each time-step, each node updates its internal state to be a linear combination of the states of the nodes in its neighborhood. We show that this causes the entire network to behave as a linear dynamical system, with sparsity constraints imposed by the network topology. We then provide a numerical design procedure to determine the appropriate linear combinations to be applied by each node so that the transmissions of the nodes closest to the actuators will stabilize the plant. We also show how our design procedure can be modified to maintain mean square stability under packet drops in the network.

Evaluation of an existing bus network using a transit network optimisation model: a case study of the Hiroshima City Bus network

Abstract: This study evaluates an existing bus network from the perspectives of passengers, operators, and overall system efficiency using the output of a previously developed transportation network optimisation model. This model is formulated as a bi-level optimisation problem with a transit assignment model as the lower problem. The upper problem is also formulated as bi-level optimisation problem to minimise costs for both passengers and operators, making it possible to evaluate the effects of reducing operator cost against passenger cost. A case study based on demand data for Hiroshima City confirms that the current bus network is close to the Pareto front, if the total costs to both passengers and operators are adopted as objective functions. However, the sensitivity analysis with regard to the OD pattern fluctuation indicates that passenger and operator costs in the current network are not always close to the Pareto front. Finally, the results suggests that, regardless of OD pattern fluctuation, reducing operator costs will increase passenger cost and increase inequity in service levels among passengers.

Integrated bus controller and power supply device for use in a process control system

Abstract: An integrated bus controller and power supply device includes a typical or standard bus controller and a bus power supply disposed in a common housing, the size and external configuration of which may match a standard bus controller device associated with a typical I/O communication network. The bus controller may store and implement one or more control routines using one or more field devices connected to the I/O communication network while the bus power supply generates and provides the appropriate power signal to the bus of the I/O communication network, the power signal being used to power the field devices connected to the I/O communication network. The integrated bus controller and power supply device can be easily connected to the bus of the I/O communication network to provide both bus controller functionality and bus power supply functionality on the I/O communication network, without the need of configuring and attaching separate, dedicated bus controller and power supply devices to the bus and having to wire these devices together using multiple different terminal blocks.

Power sequencing approach to fault isolation in dc systems: Influence of system parameters

Abstract: We show that medium-voltage dc power buses can be protected against short circuit faults by coordinating the action of a converter that supplies power to the bus with the action of contactors that are used to reconfigure the bus connections. Following a fault, the bus is de-energized (so there is no large current to interrupt), one or more contactors are reconfigured, and the dc bus is then reenergized. For a typical industrial dc bus, we show that it is possible to execute this de-energize-reconfigure-re-energize process 10 times faster than an AC bus can be protected and reconfigured using traditional circuit breakers. We show how the de-energizing and reconfiguring times depend on the output capacitance of the main converter and on the distance to the fault, and we show how to size each hold-up capacitor so that loads on unfaulted circuits can ride through the process uninterrupted.

Bus Network Planning for Transfers and the Network Effect in Melbourne, Australia:

Abstract: Although passengers dislike transferring, efficient transit systems should facilitate transfers to provide auto-competitive citywide access. This paper reviews bus transfer behavior in Melbourne, Australia, to understand causal factors. It also explores network effects: high ridership associated with frequent services or simple (grid) networks or both. Half of bus users make transfers, mostly to rail. The number of tram and bus transfers is generally low; however, in inner and central business district areas where trams run, they dominate. The young, students, males, commuters, and riders with periodical or full-fare tickets have high bus transfer rates. Middle-aged and older groups, off-peak riders, riders on shopping trips, and concession ticket holders have lower rates. Weekday peak hour commuters have high transfer rates. Frequent or longer-distance bus route types, simpler or straight route alignments, commuter services, and routes that require transfers have high transfer rates. Schedule coordinatio...

Definition of wakeup bus messages for partial networking

Abstract: A method of encoding a digital bus message information, in particular a wake-up bus message information or configuring data, on a bus system, the method comprising: encoding a predetermined part of digital bus message information bits by means of sub-patterns in a stream of line symbols on at least one bus line, wherein sub-patterns consist of successive dominant and recessive phases, comprised of recessive and dominant line symbols, wherein a recessive phase is comprised of at least two recessive line symbols in order to establish a ratio of successive dominant and recessive phases that corresponds to a value of the predetermined part. A respective digital bus message, particularly for use on a bus system, is to be encoded in accordance with the method. Further, a bus node for a system bus having a plurality of stations that are coupled together by means of an arrangement of bus lines, comprises decoding circuitry configured for an analysis of sub-patterns in a stream of data on at least one bus line, and analysing circuitry configured to detect encoded digital bus message information, in particular a wake-up bus message information or configuring data, transmitted in a stream of line symbols on the bus system, wherein the digital bus message information is encoded in accordance with the method.

Bus arbitration circuit and bus arbitration method

Abstract: Provided is a bus arbitration circuit including: a fixed priority determination circuit that grants a bus use right to an access request from a higher priority bus master among access requests from a plurality of bus masters; and a determination adjustment circuit that determines whether or not to assert the access request from the plurality of bus masters to the fixed priority determination circuit. The determination adjustment circuit masks an access request from a bus master which is granted the bus use right, for a given period of time, when the access request from the bus master which is granted the bus use right and an access request from a bus master which is not granted the bus use right compete with each other.

Switched FlexRay: Increasing the effective bandwidth and safety of FlexRay networks

Abstract: With the continued demand for more and innovative functions in series automobiles, significantly higher data-rates and more reliable communication are necessary than traditional automotive bus systems, e.g., the controller area network (CAN), provide. In this paper, we present a novel hardware device for FlexRay networks, which splits the bus into separate branches and operates as a selective central switch.

Isolated communication bus and related protocol

Abstract: A system includes a master device and multiple slave devices. The system also includes multiple bus interfaces forming a communication bus that couples the master and slave devices. Each bus interface includes a primary interface unit configured to communicate over first and second buses, where the first and second buses form a portion of the communication bus. Each bus interface also includes a secondary interface unit configured to communicate with the primary interface unit and to communicate with one of the slave devices over a third bus. Each bus interface further includes an isolator configured to electrically isolate the primary interface unit and the secondary interface unit. The primary interface unit is configured to receive multiple commands over the first bus, execute a first subset of commands, transmit a second subset of commands over the second bus, and transmit a third subset of commands over the third bus.

Summarisation in a multi-domain network

Abstract: A multi-domain network (10) comprises domains (AS A - AS E) of different network technology types. A network domain (AS A) comprises a plurality of network nodes (12, 14) connected by links (13) and comprising border nodes (12) which connect with other network domains (AS B, AS C, AS D). In a first domain (AS A) of a first technology type, a method comprises determining an intra-domain topology of the nodes (12, 14) and links (13) of the domain by collecting values of at least one network topology parameter of the first technology type. The method determines a summarised intra-domain topology of paths between border nodes (12) of the domain which is described using values of at least one summarised network topology parameter. Values of the summarised network topology parameter are derived from the values of the network topology parameter of the intra-domain topology of the first technology type. The summarised network topology parameter is part of a common set of network topology parameters for advertising between domains comprising apparatus of different technology types. A domain can comprise multiple layers of different technology type.

A reconfigurable architecture for multicore systems

Abstract: Various studies concluded that bus-based multiprocessor architectures outperform Network-on-Chip (NoC) architectures when the number of processors is relatively small. On the other hand, NoC architectures offer distinct performance advantages when the number of processors is large. This led to recent proposals for hybrid architectures where each node in a mesh-style packet-switched NoC architecture contains a bus-based subsystem with a small number of processors. Experimental results using select benchmarks demonstrated that these hybrid architectures offer superior performance when compared with purely bus based or purely NoC style architectures. Our studies indicate that while a hybrid architecture is preferable, the optimal number of processors on each bus subsystem varies based on the application. This number appears to vary between 1 and 8 depending on the communication requirements of the application. Further, various applications simultaneously executing on the same system require differing numbers of processors on each bus-based subsystem to minimize the overall throughput time. In this paper, we present a new reconfigurable NoC architecture which allows scalable bus-based multiprocessor subsystems on each node in the NoC. Following configuration, the system provides a multi-bus execution environment where each processor is connected to a bus and the bus-based subsystems communicate via routers connected in a mesh-style configuration. The system can be reconfigured to vary the number of bus subsystems and the number of processors on each subsystem. Each processor contains a Level 1 (L1) cache and each bus, connected to a router, has access to a Level 2 (L2) cache. The L2 caches distributed across the network together form a large virtual L2 that can shared by all the processors in the system via the router network. We present the architecture in detail, discuss a configuration algorithm, and discuss experimental results (using the NS2 and SIMICS simulators) on standard and synthetic benchmarks indicating the performance advantages of the proposed architecture.

Bus bridge from processor local bus to advanced extensible interface

Abstract: Disclosed is a method of processing a read/write request conforming to the PLB bus protocol and a bus bridge from PLB bus to AXI bus, the method comprising: receiving the read/write request conforming to the PLB bus protocol without waiting for an acknowledgement of successful execution of a previous read/write request conforming to the PLB bus protocol; buffering the read/write request conforming to the PLB bus protocol; mapping the buffered read/write request conforming to the PLB bus protocol to a read/write request conforming to a AXI bus protocol; and outputting the mapped read/write request conforming to the AXI bus protocol. The method and the bus bridge enable IP modules conforming to PLB bus protocol and AXI bus protocol to communicate and perform transaction mapping during communication, to guarantee that all the transactions are performed in an order desired by the PLB device, and improve communication efficiency of the SoC.

Integrated Fault Tolerant System for Automotive Bus Networks

Abstract: In automotive bus networks all the electronic components are interconnected to transmit and receive signals. The number of vehicles equipped with electronic components is increasing rapidly by replacing traditional mechanical and hydraulic systems. Nowadays most cars are functioning properly via many Electronic Control Units (ECUs), sensors and actuators, among which more than 2500 electronic signals are exchanged. There are several bus systems that have been developed for automotive bus systems to satisfy the different requirements of automotive applications: Local Interconnection Network (LIN), Controller Area Network (CAN), FlexRay and Media Oriented System Transport (MOST). However, there are more demands of combining these different bus networks in order to increase the efficiency and safety of the vehicle systems. The integrated automotive bus system, which communicates with software/hardware components on the different bus systems in a car, is more challenging problem. The discussion on how to interconnect those automotive bus networks in a fault tolerant way is addressed in the paper.

Communication slave and communication network system

Abstract: In a communication network system in which a master and a plurality of communication slaves are coupled through a high-potential side bus and a low-potential side bus in a daisy-chain manner, each of the communication slaves includes a control circuit, a resistance element, and a potential difference detecting portion. The control circuit controls communication with the master. The resistance element is inserted into the high-potential side bus at a portion located downstream of a point where the control circuit is coupled with the high-potential side bus. The potential difference detecting portion detects a potential difference between an upstream terminal of the resistance element and the low-potential side bus. The control circuit sets an ID value for communicating with the master in accordance with the potential difference detected by the potential difference detecting portion.

Development of bus location system using smart phones

Abstract: Route bus system is the fundamental transportation device for aged people and students, and has an important role in every province. However, passengers decreases year by year, therefore the authors have developed the shortest path searching system called ”Bus-Net” as a web application to sustain the public transport. But traditional Bus-Net can't inform passage information on a location of a running bus, and does not correspond to the case when the bus is delayed by the road situation. Then, we develop a bus location system that informs a location of a running bus and bus stop passage information. In addition, we develop an algorithm that estimates delay of the bus.

Power line communication system with dc power bus

Abstract: A power line communication system with DC power bus includes a power supply source, a capacitive smoothing means for smoothing the electrical voltage delivered by the source to the bus, at least one distribution box supplied by the bus and dedicated to at least one item of equipment, and an electrical current coupler of high-frequency data-carrying signals and a data modem, which are attached to the distribution box and to at least one supply line of an item of equipment.

Management techniques for electric power generation equipment

Abstract: A method for controlling power generation equipment, including bringing a generator online into a shared power bus environment, is described. The method includes determining whether the shared power bus is currently active, and whether a voltage determination fault is present with respect to a specific generator. Where the shared power bus is inactive and no fault is present, the generator is brought online in response to a load request. Where the shared power bus is active, the generator is synchronized with the shared power bus before the generator is brought online.

Load sharing architecture for redundant channel controllers

Abstract: A redundant, multi-source architecture provides output loads access to each of the plurality of power sources. The architecture includes at a least a first power bus and a second power bus. A plurality of loads are connected to the first power bus and the second power bus. Redundant first and second channel controllers are connected to receive power from the first power bus and the second power bus, respectively, wherein one of the first and second channel controllers is designated as the active channel controller. The active channel controller allocates power from both the first power bus and the second power bus to each of the plurality of loads.

Method and device for waking users of a bus system and corresponding users

Abstract: An apparatus for waking up users of a CAN bus system, wherein a sensing element, in particular a counter, is provided which senses at least one predefined signal property of the signals transmitted on the bus system and initiates the further wakeup operation when a predefined number is reached with reference to the signal property, the data stream of the CAN bus itself being used as a clock for detecting the signal property.

C302-model gateway control unit

Abstract: The invention relates to a C302-model gateway control unit characterized in that a C302 model adopts a bus structure with three CANs (Controller Area Networks) comprising a power CAN, a comfortable information CAN and an instrument diagnosis CAN, and the speeds are respectively 500K, 100K and 500K; a single gateway is designed as a route distribution center of messages and signals according to the Baud rate differences of the signals and the sharing and demands of the signals on each CAN; the route transformation is carried out on the messages with different speeds, the signals are packed and unpacked, and meanwhile, the route distribution center is also the network managing and monitoring center of each CAN bus; the time, the priority and the like of the information interaction among CAN systems are reasonably distributed; the evolution of the bus network from one CAN to a plurality of CANs and from an non-independent gateway to a central gateway is necessarily realized by a route device, and in other words, the development of the gateways is the necessary product for the updating and the function clarification of a network topology, thereby reducing the bus load rate of each subnetwork.

On-Chip Bus Serialization Method for Low-Power Communications

Abstract: One of the critical issues in on-chip serial communications is increased power consumption. In general, serial communications tend to dissipate more energy than parallel communications due to bit multiplexing. This paper proposes a low-power bus serialization method. This encodes bus signals prior to serialization so that they are converted into signals that do not greatly increase in transition frequency when serialized. It significantly reduces the frequency by making the best use of word-to-word and bit-by-bit correlations presented in original parallel signals. The method is applied to the revision of an MPEG-4 processor, and the simulation results show that the proposed method surpasses the existing one. In addition, it is cost-effective when implemented as a hardware circuit since its algorithm is very simple.