Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.

High density memory modules with improved data bus performance

Abstract: Data line loading on high density modules with multiple DRAMs is minimized permitting the maximum memory density of systems of otherwise limited density to be increased without an ensuing performance degradation due to data line capacitive loading. There are two parts to the solution of reducing data line capacitance to an acceptable system limit. The first part involves designing a memory module with in-line bus switches. The bus switches are placed between the module tabs (system) and random access memory devices and are either in a high impedance (off) or active state. When in the high impedance state, the effective loading of the module is that of the bit switch device. The second part of the solution is to embed logic into an application specific integrated circuit (ASIC) that monitors bus activity and controls activation of the bus switches. The bus switches become active on the falling edge of the system's RAS select line and stay active until the latter of the system's RAS or column address strobe (CAS) select lines going inactive, thereby supporting both Fast Page Mode (FPM) and Extended Data Output (EDO) operation. The circuit performs this task by decoding the system's RAS and CAS select lines and driving a signal to enable the bus switches.

DQDB-an access delay analysis

Abstract: The distributed queue dual bus is a protocol being considered by the IEEE 802.6 Working Committee for adoption as a metropolitan area network standard. Its primary function is to interconnect LANs over a high-speed physical medium (optical networks) operating at over 100 Mb/s and to support integrated traffic. Although DQDB is a totally distributed and contention-free protocol with throughput very close to one, the access delays experienced by stations vary with their position on the bus, upstream stations on a particular bus experiencing lesser delays compared to downstream stations. The results of simulation runs that compare the access delays experienced by MAC (media access control) stations at different utilization levels and at different priority levels are presented. It is noted that skewing in access delays is experienced by downstream stations. >

CAN bus termination circuits and CAN bus auto-termination methods

Abstract: CAN bus termination circuits, and CAN bus auto-termination methods are described. In one embodiment, a CAN bus termination circuit includes a first circuit in electrical communication with a CAN bus. The first circuit is configured to monitor an electrical operating parameter associated with operation of the CAN bus. A second circuit is in electrical communication with the first circuit, and is selectively enabled by the first circuit responsive to the first circuit's sensing a change in the electrical operating parameter that it is configured to monitor. When enabled, the second circuit terminates the CAN bus.

Data processing apparatus having first bus with bus arbitration independent of CPU, second bus for CPU, and gate between first and second buses

Abstract: An image processing apparatus containing a first bus, a second bus, a CPU connected to the first bus, a plurality of bus user units respectively connected to the second bus, a bus control unit connected with each of the plurality of bus user units and the CPU, and a bus connect/isolate gate unit connected with the first and second buses and the bus control unit. Each of the plurality of bus user units and the CPU contains a bus request signal sending unit for sending a bus request signal to the bus control unit when each of the plurality of bus user units and the CPU has a demand to use the second bus. The bus connect/isolate gate unit can isolate the first bus from the second bus, or connect the first bus with the second bus, under control of the bus control unit. The bus control unit receives the bus request signal from each of the plurality of bus user units and the CPU, determines one of the plurality of bus user units and the CPU, which sends the bus request signal to the bus control unit, as an acknowledged unit, sends an acknowledge signal to the acknowledged unit, makes the bus connect/isolate gate connect the first bus with the second bus when the CPU is the acknowledged unit, and makes the bus connect/isolate gate isolate the first bus from the second bus when the CPU is not the acknowledged unit.

Real time multiprocessor system having a write only data link connected to one of the ports of the memory of each of the processor nodes

Abstract: A real time data processing system consisting of a plurality of processing nodes and a write only reflective data link for transferring information containing writes only between the plurality or processing nodes. All the nodes include a bus, a processor coupled to the bus, a memory having at least two ports with one port connected to the bus and the other port connected to the data link and a sensor for sensing a write to the memory. At least one node has a VMEbus as the bus and serves as an I/O connected to one port of the memory. Further a local bus included for inputting and outputting from the memory. The local bus is connected to a third port of the memory.