Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.

Method and apparatus for overriding bus prioritization scheme

Abstract: A bus arbiter circuit for a system including a bus and a plurality of devices which can request access to the bus at various times. The bus arbiter circuit includes circuitry for receiving requests for access to the bus from those of the plurality of devices desiring access to the bus during an arbitration cycle; circuitry for arbitrating access to the bus during the arbitration cycle in response to the received requests, an outcome of the arbitration cycle being based on a corresponding priority level associated with each of the plurality of devices; circuitry for granting access to one of those devices requesting access to the bus based on the outcome of the arbitration cycle; and circuitry for increasing the corresponding priority level associated with those of the plurality of devices which requested access to the bus but which were not granted access to the bus as a result of the arbitration cycle.

Clock distribution system

Abstract: A clock distribution system for an integrated circuit comprising a plurality of regions (1, 2, 3) connected by a communications bus (12). Each region comprises a functional block (10a, 10b, 10c) and at least one bus node (14a, 14b, 14c) for connecting a respective functional block to the communications bus (12). A distributed clock signal (16) is allowed to skew between regions, but synchronised within respective regions. A predetermined clock insertion delay (20a, 20b, 20c, 22a, 22b, 22c) is inserted in each functional block and bus node.

Multiple bus interface adapter for connection to a plurality of computer bus architectures

Abstract: A multiple bus interface is provided for connection to the bus of a data processing device. It includes a common interface adapted for connection to any one of several bus architectures for operation therewith. The interface adapter includes a control interface for accepting control signals from the bus of said data processing device, an address interface for accepting address signals from the data processing device, and a data interface for accepting data signals from said data processing device. A bus identifier is provided for identifying the bus architecture of the data processing device as will as a bus protocol decoder responsive to the bus identifier. The decoder derives its input from the control interface and is adapted to produce as an output standardized local control signals derived from the data processing bus control signals for sue by a local functional device to be accessed by the data processing device.

Bus configuration and input/output buffer

Abstract: A system for signal transmission has at least one bus for the signal transmission and a reflection-prevention resistance provided on a stub connected to the bus for preventing reflection of signals at an intersection between the bus and the stub The system includes termination resistances, and a switch unit for coupling the bus to termination voltage via the termination resistances in a first mode and for disconnecting the bus from the termination voltage in a second mode

RMB-a reconfigurable multiple bus network

Abstract: The heart of a massively parallel computer is its interconnection network. In this article we present a reconfigurable multiple bas network to support circuit switching as means of communication between processors of a multiprocessor machine. The main contribution of the papers is in demonstrating the simplicity of the routing hardware whilst still providing modularity and full utilization of the multiple bus system. A comparison with major interconnection network is also presented.