Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.

Input/output (I/O) bidirectional buffer for interfacing I/O ports of a field programmable interconnection device with array ports of a cross-point switch

Abstract: A bi-directional buffer includes first and second unidirectional buffers connected for retransmitting signals in opposite directions between first and second buses. When an external bus driver pulls the first bus low, the first unidirectional buffer pulls the second bus low and generates a signal inhibiting the second unidirectional buffer from actively driving the first bus. When the external bus driver allows the first bus to return to the high logic level, the first unidirectional buffer temporarily supplies a high charging current to the second bus to quickly pull it up. Similarly, when an external bus driver pulls the second bus low, the second unidirectional buffer pulls the first bus low and generates a signal inhibiting the first unidirectional buffer from actively driving the second bus. When the external bus driver allows the second bus to return to the high logic level, the second buffer temporarily supplies a high charging current to the first bus to quickly pull it up. The bi-directional buffer includes a register for storing and reading out data representing successive logic states of a signal on the first bus, thereby providing a history of data appearing on the bus.

External expansion bus interface

Abstract: A computer bus interface suited to connecting an expansion bus to a computer's internal bus The interface is capable of selecting and deselecting any devices coupled to the expansion bus by enabling and disabling buffers which intercept signals between the expansion bus and the internal bus

Control system network structure

Abstract: The present invention imports network communication concepts into a motor and/or motion control system. The motor and/or motion control system is divided into various modules. A preferred configuration includes a motor drive control module, a user command module, and a master control module. The modules are interconnected by a simple hardware bus, such as an RS-485 bus. Communication between the modules is accomplished using a time division protocol.

Stream allocation in home networks

Abstract: A method and system for automatically allocating bandwidth on a network bus in an audio/visual network. The present invention implements an intelligent process to automatically make adequate bus bandwidth available when a request for a connection (e.g., a communication channel used to transfer data) between a source device and a sink device is received. First, the present invention determines whether a communication channel is already allocated to the source device, and if so, the connection between the source device and the sink device is made using an overlay of the existing communication channel. Otherwise, the present invention compares the required bus bandwidth capacity for the source device with the available bus bandwidth capacity. Using voluntary and forced load shedding techniques, the present invention deallocates bus bandwidth capacity allocated to one or more of the devices on the audio/visual network if the available bus bandwidth capacity is less than the required bus bandwidth capacity. The present invention allocates a new channel between the source device and the sink device when the available bus bandwidth capacity is greater than or equal to the required bus bandwidth capacity.

Fault-tolerant communications system and associated methods

Abstract: A communications system may include a plurality of communications buses, at least one bus device connected to the plurality of communications buses, and a plurality of bus controllers for sending a plurality of bus enable signals to the at least one bus device. The at least one bus device may include selection circuitry for selecting one of the communications buses based upon the plurality of bus enable signals while being tolerant of an error on at least one of the bus enable signals. First and second bus enable signals may have a same value and may be generated by a primary bus controller upon receiving power. A third bus enable signal may be generated by a redundant bus controller upon receiving power.