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Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.


Papers
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Patent
12 Aug 1999
TL;DR: In this paper, an apparatus for improving the efficiency of data transfers between devices interconnected over an on-chip system bus a multi-master computer system configuration is presented. But it does not suspend essential features of the system bus during the transaction.
Abstract: An apparatus is presented for improving the efficiency of data transfers between devices interconnected over an on-chip system bus a multi-master computer system configuration. Bus efficiency is improved by providing an apparatus for controlling a read-modify-write transaction to an address in a bus slave device that does not suspend essential features of the system bus during the transaction, namely, pipelining and transaction splitting. The apparatus includes transaction control logic in a bus master device and transaction response logic in a bus slave device. The transaction control logic provides a write barrier command from the bus master device over the on-chip system bus to the bus slave device. The transaction response logic receives the write barrier command, and precludes execution of future transactions to the address within the bus slave device until completion of the read-modify-write transaction while allowing execution of transactions to other addresses within the bus slave device to complete.

41 citations

Journal ArticleDOI
TL;DR: Four classes of valid inequalities for this MIP using combinatorial properties of the SBTP on the number of synchronizations are developed and Experimental results show that large instances are solved within few minutes with a relative deviation from the optimal solution that is usually less than 3 percent.

41 citations

Patent
04 Aug 1997
TL;DR: In this paper, a system for transferring data includes structure (i.e., hardware, software, a combination thereof) for requesting data from a second bus, which data is destined for a first bus; and structure for gaining ownership of the second bus for the purpose of transferring the data from the second to the first bus.
Abstract: A system for transferring data includes structure (i.e, hardware, software, a combination thereof) for requesting data from a second bus, which data is destined for a first bus; and structure for gaining ownership of the second bus for the purpose of transferring the data from the second bus to the first bus, which structure includes substructure for waiting a programmably variable amount of time to see if additional data is requested by the first bus, before relinquishing control of the second bus.

41 citations

Patent
16 Jul 1999
TL;DR: In this paper, the authors describe a vehicle consisting of a plurality of devices used in the operation of the vehicle, a single communication bus to which the devices are connected, and a single power bus to connect the devices.
Abstract: Electrical system in a vehicle including a plurality of devices used in the operation of the vehicle, a single communication bus to which the devices are connected and a single power bus to which the devices are connected. The devices include at least one accelerometer and/or at least one airbag initiator. The power bus provides power to the devices while the communication bus provides communications to and from the devices to, e.g., a control module. The devices are preferably provided with individual device addresses such that each device will respond only to its device address. Each bus may include a pair of wires and a single pair of wires may constitute both buses.

41 citations

Patent
04 Nov 2011
TL;DR: In this article, a logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to minimize the number of bus elements traversed between separate communication start and end points.
Abstract: A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points.

40 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202229
202192
202093
201999
2018108