Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.

Apparatus and method for implementing a wireless system-on-a-chip with a reprogrammable tester, debugger, and bus monitor

Abstract: A wireless communication system-on-a-chip (20) comprises a system bus (24), a set of fixed function processors (32) connected to the system bus (24), an embedded processor (28) connected to the system bus (24), and reconfigurable logic (30) connected to the system bus (24). The reconfigurable logic (30) supports an operational mode and a diagnostic mode. In the operational mode, the system operates to support different air interface protocols and data rates. In the diagnostic mode, the system alternately tests the system, debugs the system, and monitors bus activity within the system.

Method for transferring information between main store and input output bus units via a sequence of asynchronous bus and two synchronous buses

Abstract: In a data processing system, an input output bus unit (IOBU) is connected one end of an input output interface controller (IOIC) via an asynchronous bus. The other end of the IOIC is connected to a storage controller (SC) and an input output interface unit (IOIU) via a synchronous bus. The SC and IOIU are connected to a memory unit and an instruction processing unit. The asynchronous bus, which is comprised of three sub-buses and a control bus, conducts signals between the IOIC and an IOBU in an asynchronous handshaking manner. The synchronous bus, which is comprised of two sub-buses and a control bus, conducts signals between the IOIC and the SC/IOIU in an synchronous manner. The IOIC, interconnected between the synchronous bus and asynchronous bus, functions as a buffer between the faster synchronous bus and the slower asynchronous bus. Various operations are performed between an IOBU and the memory unit via the asynchronous bus, IOIC, synchronous bus, message acceptance operation.

Processor bus bridge security feature for network processors or the like

Abstract: Described embodiments provide a system having a bridge for communicating information between two processor buses. The bridge receives a command from a first bus, the command having an identification field and an address field. As the command is entered into a buffer in the bridge, the address field is checked against one or more addresses. If there is a match, then control bits are checked to see if the command will be allowed or not depending on the identification field value. If the command is not transferred to the second bus, a flag is set in the buffer, and an error message is returned to the first bus, and an interrupt may be generated. The control bits allow commands access to specific addresses on the second bus or deny the access depending on the command identification field. Bit-wise masking provides a range of values for identification and address field matching.

Fractional speed bus coupling

Abstract: Apparatus for enabling internal data processing logic including a number of units clocked at a first frequency to operate with an external bus operating at a second frequency that is a fraction m/n of said first frequency. A first bus is connected via readers to data latched for data transfer from the number internal units of the data processing logic to the data latches. A second bus is connected via drivers to the data latches for data transfer from internal bus units to the data latches. The data latches are connected to the external bus. A control circuit connected to the readers and drivers controls the readers and drivers to guarantee that sampling is done when logic is stable. The control circuit includes priority logic for determining priority between the units for permitting a high priority unit to transfer data on the external bus. Upon the condition that m=1 and n is any positive integer, transfer of data from the external bus to the first bus occurs at the point in time that the internal clock and the external clock are aligned. Upon the condition that m=2 and n is any positive odd integer, transfer of data from the external bus to the second bus occurs at the point in time that the internal clock and the external clock are aligned. The priority logic prevents enabling the drivers during any period during which the internal clock and the external clock are not aligned.