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Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.


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Patent
30 Oct 1991
TL;DR: In this article, a bi-directional bus repeater with two unidirectional repeaters connected for retransmitting signals in opposite directions between two buses is described. But the communication between the two repeaters is not considered.
Abstract: A bi-directional bus repeater includes two unidirectional bus repeaters connected for retransmitting signals in opposite directions between two buses. When an external bus driver pulls either bus low, one of the unidirectional bus repeaters pulls the other bus low. When the external bus driver allows the bus to rise to the high logic level, the unidirectional bus repeater temporarily supplies a high charging current to the other bus to quickly pull it up. Each unidirectional bus repeater also generates signals indicating when it is actively pulling its output bus up or down and the indicating signals inhibit one unidirectional bus repeater from actively driving its output when the other unidirectional bus repeater is actively driving its output.

37 citations

Patent
30 Jan 1996
TL;DR: In this paper, a data processing system is coupled to a first system processor and a second system processor via the same management bus, and at least one feature device is also configured to communicate system processor communications with the second processor via this management bus.
Abstract: In a data processing system, a first system processor is coupled to a first system bus. The first system processor includes a first bus controller. A second system processor having a second bus controller is coupled to a second system bus. The first bus controller is then coupled to a management bus, and the second bus controller is coupled to the same management bus. Thereafter, at least one feature device is coupled to the first system bus, the second system bus, and the management bus. The feature device is also configured to communicate system processor communications with the first system processor via the first system bus. Next, a problem that affects system processor communications over the first system bus between the feature device and the first system processor is detected. In response to detecting such a communications problem, a command is sent to the feature device via the management bus. In response to receiving the command on the management bus, the feature device is configured to communicate system processor communications with the second system processor via the second system bus, wherein the feature device continues to operate in the data processing system as a result of communicating system processor communications with the second system processor via the second system bus in the presence of a problem that affects system processor communications over the first system bus. A second management bus may be coupled to the first bus controller, the second bus controller, and the feature device for providing a redundant management bus.

37 citations

Book ChapterDOI
TL;DR: The aim of the MAS is 1) to diagnose problems in the bus lines and 2) to detect inconsistency in positioning data sent by buses to the central operator.
Abstract: In this paper, a multi-agent system (MAS) for bus transportation management is presented. The aim of our MAS is 1) to diagnose problems in the bus lines (bus delays, bus advances,...) and 2) to detect inconsistency in positioning data sent by buses to the central operator. Our MAS behaves as a Multi-Agent Decision Support System (MADSS) used by human regulators in order to manage bus lines. In our model, buses and stops are modeled as autonomous agents that cooperate to detect faults (disturbances) in the transportation network. An original interaction model called ESAC (Environment as Active Communication Support) was designed to allow nonintentional as well as direct communication. The system was implemented using ILOG RULES and was tested on data coming from the Brussels bus transportation network (STIB).

37 citations

Patent
21 Sep 2004
TL;DR: In this paper, a generic fabric interconnect system and method for providing a data path between and among nodes and processing elements within an interconnection fabric is presented, where a device accessible by a host processor for expanding access over a first bus to a second bus is provided.
Abstract: The present invention relates generally to a generic fabric interconnect system and method for providing a data path between and among nodes and processing elements within an interconnection fabric. More specifically, there is provided a device accessible by a host processor for expanding access over a first bus to a second bus, the first bus and the second bus each being adapted to separately connect to respective ones of a plurality of bus-compatible devices, each device which comprise a link, a first circuit adapted to couple between the first bus and the link, and a second circuit adapted to couple between the link and the second bus, the first circuit and the second circuit each being operated as a bridge and being operable to (a) send outgoing information serially through said link in a form different from that of the first bus and the second bus (b) approve an initial exchange between the first bus and the second bus in response to pending bus transactions having a characteristic signifying a destination across a device, and (c) allow the host processor, communicating through the first bus, to individually address different selectable ones of the bus-compatible devices on the second bus: (i) using on the first bus substantially the same type of addressing as is used to access devices on the first bus, and (ii) without first employing a second, intervening one of the bus-compatible devices on the second bus.

37 citations

Patent
29 Jun 1992
TL;DR: In this article, the authors describe a parallel computer network consisting of several units consisting of a CPU, a random access memory, and a bus control unit linked by an internal data bus.
Abstract: The parallel computer network includes several units (2) consisting of a CPU (3), a random-access memory (4) and a bus control unit (5) linked by an internal data bus (6). The units are interconnected by a data transmission rail (7). The bus control unit and CPU feature an additional connection for exchange of status information so that the CPU can have access to data from any unit (2) of the network. The RAMs are protected against unauthorised access by association of individual storage cells with additional control stores. ADVANTAGE - Data exchange between individual components of the network is performed without the programmer's intervention and with automatic data synchronisation.

37 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202229
202192
202093
201999
2018108