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Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.


Papers
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Patent
Stephen S. Pawlowski1
26 Sep 1995
TL;DR: In this paper, a method and apparatus for tracking transactions in a pipelined bus includes a bus state tracking queue and control logic, coupled with the bus tracking queue, which updates the status of the plurality of transactions in the bus-state tracking queue as the transactions progress through the pipeline.
Abstract: A method and apparatus for tracking transactions in a pipelined bus includes a bus state tracking queue and control logic. The bus state tracking queue maintains a record of bus transaction information for each of a plurality of transactions pending on the bus. The control logic, coupled to the bus state tracking queue, updates the status of the plurality of transactions in the bus state tracking queue as the transactions progress through the pipeline.

37 citations

Patent
30 Sep 1982
TL;DR: A fault-tolerant computer system as mentioned in this paper provides information transfers between the units of a computing module, including a processor unit and a memory unit and one or more peripheral control units on a bus structure common to all the units.
Abstract: A fault-tolerant computer system (10) provides information transfers between the units of a computing module, including a processor unit (12) and a memory unit (16) and one or more peripheral control units (20, 24, 28), on a bus structure (30) common to all the units. Information-handling parts of the system, both in the bus structure and in each unit, can have a duplicate partner (14, 18, 22). Error detectors check the operation of the bus structure and of each system unit to provide information transfers only on fault-free bus conductors and between fault-free units. The computer system can operate in this manner essentially without interruption in the event of faults by using only fault-free conductors and functional units. Arbitration circuits of unusual speed and simplicity provide units of the computing module with access to the common bus structure according to the priority of each unit. The units of a module check ncoming and outgoing signals for errors, signal other module units of a detected error, and disable the unit from sending potentially erroneous information onto the bus structure.

37 citations

Patent
14 Jan 1994
TL;DR: In this paper, an improved signaling protocol for use in a multiprocessor system enables concurrent access to a common system bus during an I/O bus access, without introducing complexities into the system bus architecture which might otherwise reduce the overall bus bandwidth increase.
Abstract: An improved signaling protocol for use in a multiprocessor system enables concurrent access to a common system bus during an I/O bus access. This reduces the system bus idling time without introducing complexities into the system bus architecture which might otherwise reduce the overall bus bandwidth increase. The improved bus architecture uses a system generated I/O bus busy (IOBUS-- BSY-) signal to indicate to all of the processors that the I/O bus is in use and that all other I/O requests must be held until the current transaction is completed. By preventing the other processors from executing an I/O request, the system bus does not have to be remain idle and can be used for memory-to-processor and for processor-to-processor transactions while the I/O bus is in use. By reducing the amount of time that the system bus is idle, the overall system bus performance is greatly increased.

37 citations

Patent
29 Sep 1995
TL;DR: In this article, a bridge coupling a primary bus to two secondary buses is presented, which supports the execution of a transaction initiated by a bus master coupled to either one of the secondary buses to a target upstream of the bridge.
Abstract: A bridge coupling a primary bus to two secondary buses. The bridge contains three interfaces, one for the primary bus and the other two for the two secondary buses. Control circuitry is included within the bridge to support the execution of a transaction initiated by a bus master upstream of the bridge to a target downstream of the bridge. The bridge also supports the execution of a transaction initiated by a bus master coupled to either one of the secondary buses to a target upstream of the bridge.

37 citations

Patent
13 Nov 1984
TL;DR: In this article, an apparatus for providing masterless collision detection in a communication network includes a distinct data transmission bus and a distinct collision detection reference bus, which is monitored by each element to ascertain the existence of a change in the voltage which results in either the enabling or disabling of data transmission on the transmission bus by that element.
Abstract: An apparatus for providing masterless collision detection in a communication network includes a distinct data transmission bus and distinct collision detection reference bus. A voltage on the reference bus is monitored by each element to ascertain the existence of a change in the voltage which results in either the enabling or disabling of data transmission on the transmission bus by that element.

37 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202229
202192
202093
201999
2018108