Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.

Global access bus architecture

Abstract: Global access bus architecture includes a master request bus and a slave request bus separated from each other and pipelined. The global access bus architecture includes packet input global access bus software code for flow of data packet information from a flexible input data buffer to an analysis machine, packet data global access bus software code for flow of packet data between a flexible data input bus and a packet manipulator, statistics data global access bus software code for connection of an analysis machine to a packet manipulator, private data global access bus software code for connection of an analysis machine to an internal memory engine, lookup global access bus software code for connection of an analysis machine to an internal memory engine, results global access bus software code for providing flexible access to an external memory, and results global access bus software code for providing flexible access to an external memory.

System and method for dynamic bus access prioritization and arbitration based on changing bus master request frequency

Abstract: In a computer system having a plurality of devices coupled to a bus, the plurality of devices having a bus master mode allowing a selected one of the devices to function as a bus master and adapted to request designation as a bus master, an arbitration circuit and method of arbitration for determining which one of the plurality of devices is to function as the bus master when two of the plurality of devices coincidentally request the designation. The arbitration circuit comprises: (1) a tabulation circuit for tabulating a relative number of times each of the plurality of devices requests designation as bus master of each of the plurality of devices and (2) a comparison circuit coupled to the tabulation circuit for granting only one of the coinciding requests as a function of the relative number of times each of the plurality of devices requests designation as bus master to thereby allow a bus master priority level between the plurality of devices to change as a function of the relative request activity of the plurality of devices.

Resolving the fairness issues in bus-based optical access networks

Abstract: Packet-based optical access ring is becoming a promising solution in metropolitan networks. Its performance depends mainly on how optical resource sharing takes place among the different competing access nodes. This network architecture has mostly been explored with regard to synchronous transmission, i.e., slotted wavelength-division multiplexing (WDM) ring. However, in this paper, we focus on the performance of asynchronous transmission-based networks with variable packet sizes. Analytical models are presented in an attempt to provide explicit formulas that express the mean access delay of each node of the bus-based optical access network. We prove that in such a network, fairness problems are likely to arise between upstream and downstream nodes sharing a common data channel. Furthermore, we show that sharing the channel's available bandwidth fairly but arbitrarily between access nodes, as in slotted WDM rings, does not resolve the fairness problem in asynchronous system. In this regard, we exhibit the inherent limitations of the token bucket access rate-based algorithm once applied to asynchronous transmission bus-based networks. To alleviate the aforementioned problem, we device a new strategy called traffic control architecture using remote descriptors. The proposed solution is based on a preventive mechanism to grant access to the shared resource. As illustrated in this paper, the proposed solution alleviates the performance degradation and the resource underutilization, while achieving fairness among bus nodes.

Bidirectional tri-state data bus buffer control circuit for delaying direction switching at I/O pins of semiconductor integrated circuit

Abstract: A data bus control circuit is formed on a single semiconductor integrated circuit that includes input/output terminals for external data exchange and a plurality of functional blocks including a CPU. A bi-directional bus buffer buffers data sent over a data bus between the CPU and the input/output terminals. The signal propagation direction of the bus buffer is determined according to a logic level of a read control signal supplied from the CPU.

Dual domain data processing network with cross-linking data queues and selective priority arbitration logic

Abstract: A two domain network linking a first and second data processing system enables efficient data transfers between modules in the first system and modules in the second system through linkage by bus exchange modules having message queues and snoop-write address queues in each domain. Each system also allocates bus access using a selectively adjusting bus access priority arbitration logic unit. The Snoop-Write address queues in each bus exchange module can temporarily hold a sequence of Write OP addresses snooped from one domain for invalidation in another domain without requiring the bus exchange module to dominate its access priority over other requesting modules.