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Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.


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Patent
13 Mar 2013
TL;DR: In this article, a communication bus system with a plurality of isolatable segments and a bus master coupled to a first end of the communication bus is described, where the bus master is configured to couple to a second end and decouple from the second end based on a selection signal.
Abstract: A communication bus system is provided. The communication bus system includes a communication bus having a plurality of isolatable segments and a bus master coupled to a first end of the communication bus. The bus master is configured to couple to a second end of the communication bus and to decouple from the second end of the communication bus based on a selection signal. A method for operating a communication bus is also disclosed.

35 citations

Journal ArticleDOI
TL;DR: This work builds a community-based backbone by applying community detection techniques and proposes a two-level routing scheme which operates over the backbone, and develops a probabilistic model to analyze the message delivery latency of CBS.
Abstract: Compared to general vehicular systems, bus systems have advantages including wide coverage, fixed routes, and regular service. Inspired by these unique features of the bus systems, we propose to use the bus systems as routing backbones of VANETs. In this work, we present a Community-based Bus System (CBS) which consists of two components: a community-based backbone and a routing scheme over the backbone. The backbone construction is a one-off operation which is done offline while the routing is done online in individual buses. We build a community-based backbone by applying community detection techniques and propose a two-level routing scheme which operates over the backbone. The proposed routing scheme performs sequentially in the inter-community level and the intra-community level, and is able to support message delivery to both buses and specific locations/areas. We develop a probabilistic model to analyze the message delivery latency of CBS. The average error of the analytically-derived latency is shown to be 8.9 percent of the latency derived from the real traces. Extensive experiments are conducted on real-world traces from the Beijing bus system and the Dublin bus system and the results show that CBS can significantly lower the delivery latency and improve the delivery ratio, compared to the existing solutions. CBS is a general solution which is applicable to any bus-based VANETs.

35 citations

Patent
30 Oct 2002
Abstract: A data processing system (100) comprises a system bus (120), a plurality of devices (110, 150, 160, 170) coupled to the system bus (120), a bus monitor circuit (140), and a clock generator (130). The plurality of devices (110, 150, 160, 170) includes at least one bus master (110, 150) which is capable of performing accesses on the system bus (120). The bus monitor circuit (140) is coupled to the at least one bus master (110, 150), and has an output for providing a bus idle signal to indicate that no bus master is attempting to perform an access on the system bus (120). The clock generator (130) has an output coupled to at least one of the plurality of devices (110, 150, 160, 170) and provides a bus clock signal having a first frequency when the bus idle signal is inactive and having a second frequency lower than the first frequency when the bus idle signal is active.

35 citations

Patent
21 Mar 1995
TL;DR: A programmable multi-level bus arbitration apparatus for computer systems is described in this paper, which implements dynamic arbitration for the grant of control over a system bus by one of a number of bus master devices.
Abstract: A programmable multi-level bus arbitration apparatus for computer systems which implements dynamic arbitration for the grant of control over a system bus by one of a number of bus master devices. A number of programmable restricters each receive a system bus request signal issued by a corresponding one of the bus master devices competing for the control over the system bus. The restricters block or relay the bus request signal. A programmable priority arbiter receives an output of each of the restricters for arbitration to grant control of the system bus to a selected one of the bus master devices based on a pre-programmed priority scheme. A communication protocol handler receives and monitors the status of the bus enable signal for generating a bus busy signal to control the issuing of a verified bus request signal by one of the restricters or the blocking of the bus request signal based on the status of the bus busy signal.

35 citations

Patent
Carl A. Bender1, Gerard M. Salem1, Richard A. Swetz1, Singpui Zee1, Ben J. Nathanson1 
05 Apr 1994
TL;DR: In this paper, an apparatus for transferring data between a main processor and its memory and a packet switch includes a first bus coupled to the main processor, a bidirectional first-in-first-out (FIFO) buffer coupled between the first bus and a second bus, a second direct memory access (DMA) engine coupled between a FIFO buffer and the second bus for transfer data between the buffer and DMA engines.
Abstract: An apparatus for transferring data between a main processor and its memory and a packet switch includes a first bus coupled to the main processor and its memory, a bidirectional first-in-first-out (FIFO) buffer coupled between the first bus and a second bus, and having a first port connected to the first bus and a second port connected to the second bus, a communications processor, coupled to the second bus, a memory operatively coupled to the second bus, a first direct memory access (DMA) engine coupled between the first bus and the FIFO buffer for transferring data between the main processor and the FIFO buffer, a second direct memory access (DMA) engine coupled between the FIFO buffer and the second bus for transferring data between the FIFO buffer and the second bus, and a packet switch interface, operatively coupled between the second bus and the switch, for interfacing the second bus to the switch, wherein packets are communicated between the memory of the main processor and the switch in accordance with the communication protocol, and wherein the first and second DMA engines transfer data for the packets independently of each other.

35 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202229
202192
202093
201999
2018108