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Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.


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Patent
06 Aug 2001
TL;DR: In this paper, a bus device (2') that has recently been connected to a bus system is first addressable at a pre-set address (126) by a bus master (1) who transmits a new address (x) and an identification (k) to the bus device(2').
Abstract: A bus device (2') that has recently been connected to a bus system is first addressable at a pre-set address (126). A bus master (1) transmits a new address (x) and an identification (k) to the bus device (2'). The bus device (2') compares the transmitted identification (k) with an identification (k') that has been stored in the bus device (2') and assumes the transmitted new address (x), if the transmitted identification (k) corresponds with the identification (k') that has been stored in the bus device (2'). The bus device (2') is then addressable at the new address (x).

35 citations

Journal ArticleDOI
TL;DR: These strategies are shown to provide a complete flexibility in tuning the number of installments that can be used per load during the distribution process so as to meet the objective of scheduling multiple divisible loads on bus networks.

35 citations

Patent
01 Nov 1985
TL;DR: In this paper, a transmission-economized serial bus protocol comprising at least one eight-bit word and at least an operation code and a subargument was proposed, and an error detection device was provided comprising an even parity bit.
Abstract: A transmission-economized serial bus protocol comprising at least one eight-bit word further comprising at least an operation code and a subargument (Fig. 2). The operation code and subargument comprise, respectively, either a start-of-message character or a start-of-reply character and either a device destination address or the device's source addresse (Fig. 3). Further, an error detection device is provided comprising an even parity bit. Moreover, there is provided an optimized method of bus contention comprising monitoring the bus (230) for an idle or busy bus condition and either attempting an asynchronous bus access if the bus is idle or synchronously attempting a prioritized retry after a busy bus condition is sensed, after a bus access collision is sensed, and upon initial power-up, synchronized to the current message completion. The prioritization comprises a constant time delay plus a bit-time delay proportional to an accessing device's address identification (Fig. 5). Finally, there is provided an optimized method of inter-device (120, 140, 150, 180, 190, 200) message addressing and handshaking in a multi-access, bussed system, each device having a source and destination address, comprising addressing a message to a destination address and awaiting the addressed destination device to acknowledge by echoing its corresponding source address and also monitoring the bus (230) for an announcement of a source addressed event and performing a function accordingly.

35 citations

Patent
01 Jun 1995
TL;DR: In this paper, a processor capable of selecting between a write-back and a writethrough mode of operation includes a bus interface unit for transferring information across the external bus and a local cache memory coupled to the bus interface units for storing information received from the bus interfaces.
Abstract: A processor capable of selecting between a write-back and a write-through mode of operation includes a bus interface unit for transferring information across the external bus. A local cache memory is coupled to the bus interface unit for storing information received from the bus interface unit. The processor also includes a control unit coupled to the cache memory and the bus interface unit. The control unit is operable to restart an interrupted operation from a point of interruption. A storage device coupled to the control unit stores a value corresponding to the point of interruption of the operation.

35 citations

Proceedings ArticleDOI
13 Mar 2001
TL;DR: One of the key-enablers of the methodology, the universal communication model (UCM) is defined at a level of abstraction that allows accurate estimates of the performance including the latencies over the bus network, and good simulation performance.
Abstract: In this paper, we present a virtual integration platform based design methodology for distributed automotive systems. The platform, built within the 'Virtual Component Co-Design'' tool (VCC), provides the ability of distributing a given system functionality over an architecture so as to validate different solutions in terms of cost, safety requirements, and real-time constraints. The virtual platform constitutes the foundation for design decisions early in the development phase, therefore enabling decisive and competitive advantages in the development process. This paper focuses on one of the key-enablers of the methodology, the universal communication model (UCM). The UCM is defined at a level of abstraction that allows accurate estimates of the performance including the latencies over the bus network, and good simulation performance. In addition, due to the high level of reusability and parameterization of its components, it can be used as a framework for modeling the different communication protocols common in the automotive domain.

35 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202229
202192
202093
201999
2018108