Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.

Circuits, systems and method for address mapping

Abstract: An information processing system 400 includes a subsystem 402 having a processing resource 404 and a bus interface 403. An active logic mapping signal is presented to a mapping input bus interface 403. The system also includes a master processing device which is operable to write at least some bits of a starting address into bus interface 403, determine an ending address for subsystem 402 and lock subsystem 402.

Method of round robin bus arbitration

Abstract: An arbitration unit contains a method of arbitration which includes distributed arbitration, a priority mechanism to support different classes of traffic, a unique arbitration ID bits for each module, a round robin arbitration within a given priority level to produce fair access to a bus 36, an arbitration timeout, and a bandwidth allocation between priority levels. The method of round robin bus arbitration includes the steps of providing a plurality of modules, providing a bus having a plurality of data lines, the bus connecting the plurality of modules, the bus having an arbitration unit, setting the bus to a wait state, signaling a first bus request to the bus by a first module needing to transmit a first plurality of data packets on to the bus, the first module having a first module priority level and a first unique arbitration number, signaling a second bus request to the bus by a second module needing to transmit a second plurality of data packets on to the bus, the second module having a second module priority level and a second unique arbitration number, establishing a bus priority according to a comparison of the first module priority level and the second module priority level, asserting the first unique arbitration number on the bus by the first module, asserting the second unique arbitration number on the bus by the second module, determining whether the first module and the second module have been waiting for the bus, comparing the first unique arbitration number and the second unique arbitration number, scheduling transmission of data packets in response to the steps of determining and comparing, and repeating the steps of setting, signaling, establishing, asserting, determining, comparing, and scheduling.

BMSYN: Bus Matrix Communication Architecture Synthesis for MPSoC

Abstract: Modern multiprocessor system-on-chip designs have high bandwidth constraints which must be satisfied by the underlying communication architecture. Traditional hierarchical shared bus communication architectures can only support limited bandwidths and are not scalable for very high-performance designs. Bus matrix-based communication architectures consist of several parallel busses which provide a suitable backbone to support high-bandwidth systems but suffer from high-cost overhead due to extensive bus wiring inside the matrix. Manual traversal of the vast exploration space to synthesize a minimal cost bus matrix that also satisfies performance constraints is practically infeasible. In this paper, we address this problem by proposing an automated approach for synthesizing a bus matrix communication architecture, which satisfies all performance constraints in the design and minimizes wire congestion in the matrix. To validate our approach, we consider several industrial strength applications from the networking domain and show that our approach results in up to 9times component savings when compared to a full bus matrix, and up to 3.2times savings when compared to a maximally connected reduced bus matrix, while satisfying all performance constraints in the design.

A transparent bridge between buses of a computer system and a method of interfacing the buses to operate as a single logical bus

Abstract: A bridge and a method for interfacing a plurality of buses with which the bridge provides electrical isolation between the buses but is transparent so that the plurality of buses is viewed by software as a single logical bus. Transaction cycles initiated on one bus are reflected on the other bus. A speculative start of a transaction cycle on a secondary bus immediately after the transaction cycle has been started on the first bus provides a significant savings in time to complete transactions in which the target of the transaction is on the secondary bus.

Current mode data or power bus

Abstract: A current mode data or power bus which provides communication between two or more terminal devices over a common, single-channel medium. The data bus comprises a pair of wires, twisted to form a succession of loops and short-circuited at both ends, together with an arbitrary number of bus couplers, one for each terminal. The bus couplers are formed by separate, disengageable core elements. Each bus coupler is inductively coupled to the twisted wire pair by inserting one or more core legs of the bus coupler through adjacent loops in the twisted wire pair; each wire loop around a core leg then constituting a one-turn transformer winding of the coupler. In this manner, separate terminals can be readily coupled to or decoupled from the current mode data communication bus without the need for making spliced, galvanic connections. This bus configuration is readily adaptable to single or multiphase power transmission. And, in either case, the bus configuration provides excellent electromagnetic interference rejection properties.