Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.

Automatic addressing on bus systems

Abstract: The invention relates to a method for automatically allocating addresses to control devices (3-6) in a means of communication, which are connected to a bus system (1). According to said method, the control devices (3-6) exchange data via a common data bus line (2) by means of transmitting/receiving units (10) and simultaneously access the data transmitted by means of the common data bus line (2). Also disclosed is a bus system (1) for carrying out the inventive method. The aim of the invention is to create a method and a bus system which optimize automatic address allocation in a bus system comprising a common data line. Said aim is achieved by starting an address allocation interval by means of a message on the common data bus line (2). The common data bus line (2) is then galvanically separated into individual partial sections within the address allocation interval based on said message, the control devices (4-6) that are to be addressed galvanically separating the common data bus line (2) by means of a separating means (9). In addition, the control devices (4-6) that are to be addressed set the respective transmitting unit (10) thereof to a certain transmission potential.

Local bus design

Abstract: In an IBM PC AT-compatible computer architecture, CPU-generated addresses and data for accesses to a peripheral device in the I/O address space are coupled directly to the peripheral device from the local bus, without traversing the I/O bus. Any data returned from the peripheral device is coupled directly to the local bus, also without traversing the I/O bus. No buffers are needed for communicating such address and data information between the peripheral device and the I/O bus.

Bus hang prevention and recovery for data communication systems employing a shared bus interface with multiple bus masters

Abstract: A shared bus hang prevention and recovery scheme for a data communication system is provided, where a shared bus is connected to a plurality of bus masters and corresponding slaves and located between an external bus connected to a system processor, and an internal bus connected to an internal processor. Some of the masters are associated with the external bus and others are associated with the internal bus, and one of the bus masters is a control master associated with the internal processor. The scheme utilizes a shared bus hang prevention and recovery device having a circuitry and a control code. The circuitry is timing each pending request of the control master for the shared bus and initiating bus recovery if the shared bus is hung up, when the control master exceeded a pre-determined time period allowed for waiting to acquire the shared bus control and complete the transfer on the shared bus. The control code is used for monitoring and controlling the circuitry and terminating the transfer in progress causing the shared bus hang-up. During the bus recovery the circuitry prevents bus request grants to the master attached to the external bus until the master subsequent reset, and the control program instructions initiates transfers for all pending requests for the shared bus from the control master queue. Each transfer is being timed and terminated if the shared bus is hung up again. Upon the control master queue clearing, the internal processor executes the control program instructions to reset and reinitialize all masters and slaves on the shared bus.

Device for the bus-networked operation of an electronic unit with microcontroller, and its use

Abstract: A device for bus-networked operation of an electronic unit having microcontroller has a semiconductor circuit which is supplied from a superordinate potential, and is connected between a bus protocol module of the microcontroller and the cores of a two core bus. The semiconductor circuit, which has at least two operating modes, "transmission and reception" (NORMAL) and "sleep" (SLEEP), compromises: a receiving circuit connected to the two bus cores, whose output communicates with a reception input of the bus protocol; a transmitting circuit coupled to receive the transmission output of the bus protocol function; a wake-up identification circuit connected to the cores of the two core bus, and having a wake-up input and switching means for providing, at a control output, a switch-on signal after identification of a wake-up signal from the wake-up input or from the bus, and for emitting a switch-off signal in the SLEEP mode. A voltage regulator, supplied from superordinate potential, provides a regulated output voltage to the microcontroller and to the bus protocol module. The voltage regulator has a control input which communicates with the control output of the semiconductor circuit, and is configured to switch on in the presence of the switch-on signal and to switch off in the presence of the switch-off signal,

Self-mounting bus

Abstract: In the case of a modular electrical installation, for instance a modular programmable controller, the bus is modularly configured on the modules, so that the bus is automatically propagated when the installation is assembled.