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Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.


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Patent
22 Dec 1997
TL;DR: In this article, it is recommended that input buffers associated with signals of a request and arbitration phase be maintained active and coupled to power regardless of the present transaction phase unless the computer enters a powered down mode, such as sleep, idle or standby.
Abstract: A computer is provided having a bus interface unit coupled between a CPU bus and a mezzanine bus, or PCI bus. The bus interface unit includes a plurality of input buffers which can be selectively connected and disconnected in a dynamic fashion according to active and inactive signals forwarded thereto. Signals forwarded to the bus interface unit from the CPU are classified according to the transaction phase of CPU bus activity. If signals associated with one particular transaction phase are active, then input buffers attributed to signals of other transaction phases can be deactivated. It is preferred that input buffers associated with signals of a request and arbitration phase be maintained active and coupled to power regardless of the present transaction phase unless the computer enters a powered down mode, such as sleep, idle or standby.

32 citations

Patent
13 Aug 1997
TL;DR: In this paper, the authors propose a method for supporting multiple distributed interrupt controllers, designated as bus agents, in a symmetric multiprocessing system, which method includes the steps of assigning a unique identification number to each bus agent, receiving bus requests from the bus agents over four data lines in groups of four, and granting bus ownership to a selected one of the requesting bus agents.
Abstract: A method for supporting multiple distributed interrupt controllers, designated as bus agents, in a symmetric multiprocessing system, which method includes the steps of assigning a unique identification number to each bus agent, receiving bus requests from the bus agents over four data lines in groups of four, and granting bus ownership to a selected one of the requesting bus agents. Similarly, a computer system that supports multiple distributed interrupt controllers, designated as bus agents, in a symmetric multiprocessing system, which computer system includes structure for assigning a unique identification number to each bus agent, four data lines for receiving bus requests from the bus agents in groups of four, and structure for granting bus ownership to a selected one of the requesting bus agents.

32 citations

Patent
07 Jan 1999
TL;DR: In this paper, the I2C serial bus that connects the controllers and the slave units is provided with a secondary memory containing software drivers for a variety of different types of slave units, which can be present on the bus by sending, for each type of slave unit represented by a corresponding software driver, a command via the bus using an address for the type.
Abstract: In accordance with embodiments of the invention, an electronic device including one or more controllers and one or more slave units is provided with a bus such as an I2C serial bus that connects the controllers and the slave units. The device further includes a secondary memory containing software drivers for a variety of different types of slave units, which can be present on the bus. The controller determines which types of slave units are actually present on the bus by sending, for each type of slave unit represented by a corresponding software driver in the secondary memory, a command via the bus using an address for the type. After determining which types of slave units are present on the bus, the controller loads correponding software drivers from the secondary memory into a RAM, and using the loaded software drivers to initialize the slave units present on the bus.

32 citations

Patent
28 Sep 2007
TL;DR: In this paper, a method and apparatus for a bus controller that supports a flexible bus protocol that handles pipelined, variable latency bus transactions while maintaining point-to-point (P2P) FIFO ordering of transactions in a non-blocking manner is presented.
Abstract: A method and apparatus is disclosed herein for a bus controller that supports a flexible bus protocol that handles pipelined, variable latency bus transactions while maintaining point-to-point (P2P) FIFO ordering of transactions in a non-blocking manner. In one embodiment, the apparatus includes a bus controller to receive a plurality of bus transactions at a first incoming port from a bus. The bus controller is configured to process the plurality of bus transactions in a pipelined manner, maintaining P2P FIFO ordering of the plurality of bus transactions even when the plurality of bus transactions take a variable number of cycles to complete.

32 citations

Patent
27 Jan 1986
TL;DR: In this paper, a method for implementing a token ring network on a token bus network is described, in which a node is connected to each one of a plurality of token bus nodes such that the token ring node appears to the token bus node to which it is connected as station equipment and the node bus nodes appear to the node ring node as both the next and preceding token ring nodes in a ring network.
Abstract: A method is disclosed for implementing a token ring network on a token bus network. In accordance with the invention a token ring node is connected to each one of a plurality of token bus nodes such that the token ring node appears to the token bus node to which it is connected as station equipment and the token bus node appears to the token ring node as both the next token ring node and the preceeding token ring node in a ring network. A message is transmitted from a token ring node by forming a token ring frame and transmitting the token ring frame to the next token ring node which is the token bus node to which the token ring node is connected. The token bus node encapsulates the token ring frame that it receives in a token bus frame and transmits the resulting token bus frame to a destination bus node. The destination bus node receives the token bus frame, removes the token ring frame that is encapsulated therein and forwards the token ring frame to the token ring node connected to the destination bus node.

32 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202229
202192
202093
201999
2018108