Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.

On Bus Type Assignments in Random Topology Power Grid Models

Abstract: In order to demonstrate and test new concepts and methods for the future grids, power engineers and researchers need appropriate randomly generated grid network topologies for Monte Carlo experiments. If the random networks are truly representative and if the concepts or methods test well in this environment they would test well on any instance of such a network as the IEEE model systems or other existing grid models. Our previous work [1] proposed a random topology power grid model, called RT-nested-small world, based on the findings from a comprehensive study of the topology and electrical properties of a number of realistic grids. The proposed model can be utilized to generate a large number of power grid test cases with scalable network size featuring the same small-world topology and electrical characteristics found from realistic power grids. On the other hand, we know that dynamics of a grid not only depend on its electrical topology but also on the generation and load settings, and the latter closely relates with an accurate bus type assignment of the grid. Generally speaking, the buses in a power grid test case can be divided into three categories: the generation buses (G), the load buses (L), and the connection buses (C). In [1] our proposed model simply adopts random assignment of bus types in a resulting grid topology, according to the three bus types' ratios. In this paper we examined the correlation between the three bus types of G/L/C and some network topology metrics such as node degree distribution and clustering coefficient. We also investigated the impacts of different bus type assignments on the grid vulnerability to cascading failures using IEEE 300 bus system as an example. We found that (a) the node degree distribution and clustering characteristic are different for different type of buses (G/L/C) in a realistic grid, (b) the changes in bus type assignment in a grid may cause big differences in system dynamics, and (c) the random assignment of bus types in a random topology power grid model should be improved by using a more accurate assignment which is consistent with that of realistic grids.

Method and apparatus for christening a trainline monitor system

Abstract: A method for initializing a communication network in a train including a plurality of cars, the network comprising a train bus, a train bus master on one of the cars and a train bus slave on each other car connectable to the train bus master by the train bus for communicating with the train bus master. The method includes determining whether the one car with the train bus master is located at one end of the train or is in the middle of the train. The method further includes transmitting first messages between the train bus master and each train bus slave, respectively, located in one direction for assigning an address to each train bus slave located in that one direction and acquiring data at the train bus master uniquely identifying the respective train bus slaves in that one direction. The method further includes transmitting, when the determining step determines that the one car is located in the middle of the train, second messages between the train bus master and each train bus slave, respectively, located in an other direction for assigning an address to each train bus slave located in the other direction and acquiring data at the train bus master uniquely identifying the respective slaves in the other direction.

System-on-a-chip bus architecture for embedded applications

Abstract: Increasing levels of on-chip system integration means that more functional units need to be interconnected. To limit design effort and to allow for future reuse, this interconnection should be kept as simple and generic as possible. The need to limit clock cycle times and power consumption means that bus capacitance must be as low as possible. This can be done effectively by partitioning functional units onto discrete bus connections that are jointed by bus bridges. The paper describes the evolution of ARM system chip architectures of steadily increasing complexity and details a state-of-the-art design.

High performance asynchronous bus interface

Abstract: A bus interface coupling an asynchronous bus and a slave device, such as a memory. The bus interface comprises an asynchronous bus controller and a synchronous bus controller. The asynchronous bus controller is implemented as two PAL state machines. One state machine controls the connection and disconnection phases of the bus protocol, while the other controls the data transfer phase. The synchronous bus controller controls data transfer between the bus and the slave device. The state machines are closely interlinked to each other and the synchronous bus controller allowing for increased bus efficiency.

A High-Speed Optical Multi-Drop Bus for Computer Interconnections

Abstract: Buses have historically provided a flexible communications structure in computer systems. However, signal integrity constraints of high-speed electronics have made multi-drop electrical busses infeasible. Instead, we propose an optical data bus for computer interconnections. It has two sets of optical waveguides, one as a fan-out and the other as a fan-in, that are used to interconnect different modules attached to the bus. A master module transmits optical signals which are received by all the slave modules attached to the bus. Each slave module in turn sends data back on the bus to the master module. Arrays of lasers, photodetectors, waveguides, microlenses, beamsplitters and Tx/Rx integrated circuits are used to realize the optical data bus. With 1 mW of laser power, we are able to interconnect 8 different modules at 10 Gb/s per channel. An aggregate bandwidth of over 25 GB/s is achievable with 10 bit wide signaling paths.