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Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.


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Patent
31 Aug 1999
TL;DR: In this article, a bus testing logic is built into some of the devices connected to the bus to enable these devices to perform diagnostic testing of the bus, where the bus signals produced by the devices propagate along the bus and are received by other devices.
Abstract: Bus testing logic is built into some of the devices connected to the bus to enable these devices to perform diagnostic testing of the bus. Under control of the test logic, the devices drive the bus with output voltages corresponding to a predetermined test bit pattern that is selected to cause the bus to reach a target bus utilization level. The bus signals produced by the devices propagate along the bus and are received by other devices. The received bus signals are resolved into a received bit pattern. The received bit pattern is compared with the test bit pattern used to generate the bus signals in order to detect discrepancies. In one embodiment, the devices can operate in a first mode by driving the bus in accordance with performing normal functions or in a second mode by performing diagnostic testing on the bus by driving the bus in accordance with the test bit pattern. Test patterns can be interleaved with normal bus signals. Alternatively, the test logic in the devices can arbitrate with the normal circuitry to assume control of the bus for testing purposes. In still another embodiment, a first device includes both a bus driver and a bus receiver and a second device includes logic for looping the bus signals back to the device that generated the signals.

32 citations

Proceedings ArticleDOI
22 Sep 2004
TL;DR: This paper proposes an active star topology that allows solving many of the limitations related to the first aspect by means of strong error confinement and compares bus and star topologies, analyzes related work and discusses the hub implementation and dependability properties.
Abstract: Distributed embedded systems that require real-time performance need a network capable of deterministic access delay. CAN is one such network that became widespread in recent years due to its electrical robustness, low price, and priority-based access control. However, its use in safety-critical applications has been controversial due to dependability limitations that arise from its bus topology and non-guaranteed atomic broadcast. In this paper, we propose an active star topology that allows solving many of the limitations related to the first aspect by means of strong error confinement. Nodes are interconnected through an active hub that is fully compatible with existing CAN controllers. The paper compares bus and star topologies, analyzes related work and discusses the hub implementation and dependability properties.

32 citations

Patent
09 Sep 1997
TL;DR: In this paper, a general purpose microcomputer with an upstream bus and a downstream bus is presented, where the upstream bus interfaces to an integrated multiport RAM that is shared between an upstream processor and the local processor, and possesses both upstream and local interrupts associated with dedicated locations in RAM.
Abstract: A novel architecture is based on a general purpose microcomputer with an "upstream" bus and a "downstream" bus. The upstream bus interfaces to an integrated multiport RAM that is shared between an upstream processor and the local processor, and possesses both upstream and local (downstream) interrupts associated with dedicated locations in RAM. The upstream bus can be operated in two modes, a standard (EISA) PC bus MASTER mode in which the dual port RAM is compatible with an IBM PC bus and a SLAVE mode in which the upstream bus is compatible with the downstream bus. An indefinitely long chain of such processors can be initialized by one host. Orthogonal channels (decoupled from the main upstream/downstream bus) can be used to achieve unique functionality based on host control of arrays of such processors.

32 citations

Patent
19 Mar 1999
TL;DR: In this paper, a system is described having a network, a bus and an interface coupling the network to the bus, where a host is coupled to the network and executes software to generate packets for communication on the network.
Abstract: A system is described having a network, a bus and an interface coupling the network to the bus. A host is coupled to the network and executes software to generate packets for communication on the network. A bus device is coupled to the bus. The interface and host coordinate to transport bus device packets between the host and the bus device via tunneling over the network.

32 citations

Patent
12 Jul 1976
TL;DR: In this article, a priority network utilizing a common bus coupled with a plurality of priority seeking peripheral devices is defined, such that each device will have a unique priority defined and each peripheral device is provided with an associated peripheral control unit.
Abstract: A priority network utilizing a common bus coupled to a plurality of priority seeking peripheral devices wherein a processor or any number of processors is connected to the common bus. Each successive peripheral device is connected to the common bus in increasing priority order, such that each device will have a unique priority defined. Each peripheral device is provided with an associated peripheral control unit. Each of the peripheral control units is connected in serial fashion on an enabling line with the output of the higher priority control unit providing an enabling input to the next lowest priority peripheral control unit, such that the highest priority device requesting bus access prevents all lower priority devices from gaining access to the common bus until the higher priority device has completed its data transfer.

32 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202229
202192
202093
201999
2018108