Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.

Method and apparatus for enabling data paths on a remote bus

Abstract: A method for enabling data paths including the steps of receiving a request to enable a data path on a remote bus between a first processing apparatus and a second processing apparatus, determining whether the remote bus can handle the requested data path, and enabling the data path on the remote bus if the remote bus can handle the requested data path. In addition, an apparatus for enabling data paths including an apparatus for receiving a request to enable a data path on a remote bus between a first processing apparatus and a second processing apparatus, apparatus for determining whether the remote bus can handle the requested data path, and apparatus for enabling the data path on the remote bus if the remote bus can handle the requested data path.

Method and apparatus for distributing bus loading in a data processing system

Abstract: Method and apparatus for distributing bus loading in a data processing system (11, 13, 15). In one embodiment, the present invention uses a bus loading control register bit field (90) to determine how address and data will be transferred over busses (60, 62) in order to allow more equal distribution of loads on the busses (60, 62). There is no fixed address bus or data bus. Instead, on a per cycle basis, each generic bus (60, 62) can be individually programmed to transfer address only, data only, both address and data, or neither address nor data. In one embodiment, there is a programmable address range (150-153) which corresponds to each bus loading bit field (90-93). For a bus access to a particular address range, the corresponding bus loading bit field (e.g. 90) is used to determine how address and data are transferred across the busses (60, 62).

Low power system and method for a data processing system

Abstract: Systems and methods are discussed to identify a recoverable state in a low power device. A low power device (100, 300, or 400) having an arbiter (110, 310, or 410) to grant system bus access to a plurality of bus masters is set to initiate a low power mode of operation. A low power controller (150, 350, or 450) within the low power device provides a request to the bus arbiter to initiate a low power mode. The bus arbiter stops granting bus requests to the bus masters and identifies when the system bus has processed all current bus accesses. When the system bus is idle, the bus arbiter returns a bus grant signal to the low power controller. Clocks associated with the bus masters are disabled to suspend the bus arbiters and allow less power to be consumed by the low power device.

Method for time multiplexing a low-speed and a high-speed bus over shared signal lines of a physical bus

Abstract: A method for combining a low-speed communications bus and a high-speed communications bus into a single multiplexed communications bus that supports both low-speed and high-speed operations. The multiplexed communications bus contains a low-speed state machine and a high-speed state machine. The multiplexed communications bus is controlled by the low-speed state machine and operated at low speed in order to conduct transactions between two low-speed peripheral devices, and is controlled by the high-speed state machine and operated at high speed in order to conduct transactions between and two high-speed peripheral devices. For transactions between peripheral devices having different speeds, either a buffer is used to store data between data transmission and data reception by the two devices, or the low-speed and high-speed state machines are synchronized and operationally interleaved.

A Hardware Implement of Bus Bridge Based on Single CPU and Dual Bus Architecture

Abstract: Single CPU dual bus architecture is a new kind of architecture aimed at reducing the security vulnerability of Von Neumann architecture, and it has been proved theoretically reasonable. In this paper, a bus bridge is implemented to bridge CPU and dual bus. The experiment is done and the result has proved that the architecture based on single CPU and dual bus is reasonable and effective.