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Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.


Papers
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Patent
04 Dec 2007
TL;DR: In this article, the authors provide a method for composing a device with different types of multi-processor subsystems based on expected latency times and processing bandwidths, which can operate in an independent manner.
Abstract: Aspects of the invention provide apparatuses and methods for composing a device with different types of multi-processor subsystems based on expected latency times and processing bandwidths. An apparatus may include multi-processor subsystems with different performance characteristics that interact with each other through bridge modules and a central packet network. Different types of multi-processor subsystems include a multi-point bus network, a circuit-switched network, a packet-switch network, and a shared block device. The apparatus includes a plurality of components, where each component has at least one multi-processor subsystem. The apparatus may be partitioned into different detachable parts, which can operate in an independent manner. The detachable parts may be joined so that the detachable parts can interact. A service in one multi-processor subsystem may interact with another service in another multi-processor subsystem by sending messages between the services.

29 citations

Patent
23 Mar 2004
TL;DR: In this article, a method of electrically coupling a central processing unit (CPU) of a network server to a plurality of network interface modules is proposed, which includes providing each of the plurality of NIMMs with a respective bus adapter chip.
Abstract: A method of electrically coupling a central processing unit (CPU) of a network server to a plurality of network interface modules. The method comprises providing each of the plurality of network interface modules with a respective bus adapter chip to route an I/O bus having a first format from the central processing unit to a primary side of each of the plurality of bus adaptor chips and routing another I/O bus of the first format from a secondary side of each of the plurality of bus adapter chips to respective ones of the network interface modules. The bus adapter chips also provide for arbitered access along the I/O buses and isolation of the CPU from electrical disruption when one the network interface modules is removed.

29 citations

Patent
18 Jul 1997
TL;DR: In this article, a communication bus consisting of a plurality of bus segments, each bus segment being concatenated with at least one adjacent bus portion by means of buffer registers to transfer a data item from the adjacent bus segment to the bus portion, the computer system comprising an arbitration unit to control the simultaneous access to the different segments, in a mutually exclusive way.
Abstract: Computer system comprising a communication bus, a plurality of units connected to the bus, in which the bus includes a plurality of bus segments, each bus segment being concatenated with at least one adjacent bus portion by means of buffer registers to transfer a data item from the adjacent bus segment to the bus portion, the computer system further comprising an arbitration unit to control, for each bus segment, the simultaneous access to the different segments, in a mutually exclusive way, by the units connected to each of the segments and by the buffers for concatenation of each of the segments with at least one adjacent segment.

29 citations

Patent
William B. Ledbetter1
03 Jul 1989
TL;DR: In this paper, a data processing system having a mechanism for changing communication bus mastership when a series of locked operand transfer sequences are executed is presented, where the system has at least two processors coupled via the communication bus and a bus arbiter.
Abstract: A data processing system having a mechanism for changing communication bus mastership when a series of locked operand transfer sequences are executed. The system has at least two processors coupled via the communication bus and a bus arbiter. In one form, a locked transfer end signal is provided by each processor to the bus arbiter so that if a high priority need is recognized by the bus arbiter during early execution of a plurality of locked operand transfer sequences the high priority need can be responded to by the bus arbiter before completion of all of the locked sequences. In another form, control signals are provided by the bus arbiter to each processor to accomplish the equivalent function.

29 citations

Patent
01 Aug 2006
TL;DR: In this article, an energy transmission interface for contactless energy supply of a bus subscriber, which is designed as an input/output device, is provided for the contactless connection of the bus subscriber to a data bus.
Abstract: The device (1) has an energy transmission interface (3) for contactless energy supply of a bus subscriber, which is designed as an input/output device. A data transmission interface (4) is provided for contactless connection of the bus subscriber to a data bus. The energy transmission interface includes a primary coil for inductive transmission of electrical energy to a secondary coil, which is arranged in the bus subscriber, in such a manner that the function of the data transmission interface is satisfied. An independent claim is also included for a bus subscriber with a mounting unit for mounting the bus subscriber at the device for mechanical mounting of bus subscriber of a data bus.

29 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202229
202192
202093
201999
2018108