Bus network

About: Bus network is a research topic. Over the lifetime, 7017 publications have been published within this topic receiving 97556 citations.

Dynamic access scheduling memory controller

Abstract: Bus transactions in a memory controller are scheduled by storing a set of configuration parameters that define a bus scheduling policy, generating values of a set of dynamic cost functions for each bus transaction, ordering the bus transactions in accordance with the bus scheduling policy to produce ordered bus transactions and generating a memory transaction that is derived from the ordered bus transactions. The memory controller includes one or more control registers for storing the set of configuration parameters, a bus interface operable to capture bus transactions from applications, a set of buffers operable to store the bus transactions and the set of dynamic cost functions and one or more registers operable to store the statistical data and a cost policy. The memory controller selects the order of the bus transactions based on an arbitration and selection policy and generates memory transactions to an external memory.

Self-adjusting, distributed control, access method for a multiplexed single-signal data bus

Abstract: A method of providing access to a multiplexed data bus having a plurality of data processing units coupled thereto. Each unit self-assigns sequence numbers thereto for identification purposes. The unit having the lowest sequence number obtains immediate access to the bus and may relinquish the bus by transmitting a control word, or token, with an incremented sequence number. All units receive the token but only the unit having the incremented sequence number gains access to the bus. The token passing continues through the series of sequence numbers and then recycles when no unit accepts the token (bus timeout). A newly added unit self-assigns a sequence number equal to the one transmitted prior to the bus timeout and thus acquires bus access on the next cycle. If a unit in the cycle fails, a bus timeout occurs mid-cycle and the access loop recycles. The units not gaining access to the bus during the cycle decrement their sequence numbers to close the gap, and hence gain access on the next cycle. The method allows for continuous system operation if units are added or deleted, without interrupting bus operation.

Control bus for connection of electronic devices

Abstract: A method and apparatus for a control bus for connection of electronic devices. An embodiment of a method includes coupling a transmitting device to a receiving device, including connecting a control bus between the transmitting device and the receiving device, with the control bus being a bi-directional, single-line bus. The method further includes obtaining control of the control bus for either the transmitting device or the receiving device, with the device obtaining control becoming an initiator and the other device becoming a follower. One or more control signals are converted to one or more data packets, with each of the one or more control signals representing one of multiple different types of control signals. The generated data packets are transmitted from the initiator to the follower via the control bus.

Polling of failed devices on an I2 C bus

Abstract: Polling of devices on an inter-IC (I 2 C) is provided. An expansion processor resides on a primary I 2 C bus. The expansion processor is coupled to a plurality of I 2 C sub-buses each of which may host a plurality of I 2 C devices. Data is transferred between the expansion processor and the plurality of I 2 C devices via the corresponding sub-bus according to an I 2 C protocol. Data transfer is in response to a request initiated by a bus master on the primary I 2 C bus. The bus master communicates with a target device residing on one of the sub-buses by addressing the expansion processor. The bus master informs the expansion processor of the target device by sending the expansion processor a number of the sub-bus on which the target device resides, and an address of the target device. A data stream bound for the target device is directed to the expansion processor which then echos it to the target device. Likewise, a data stream bound from the target device to the bus master on the primary I 2 C bus is transmitted to the expansion processor which then echos it to the bus master. Each of the target devices on the sub-bus can be polled to determine if they have failed. Failure of a device only affects operation of its sub-bus.

Method and system for generating a circuit design including a peripheral component connected to a bus

Abstract: Method and system for generating an electronic circuit design. A first logic block is instantiated in the design in response to user input controls. The first logic block includes parameters that specify its interface requirements. Bus interface blocks, which are parameterizable to connect a logic block to a bus, are provided in a library. Bus interface blocks that connect the first logic block to the bus are instantiated in the design, and the bus interface blocks are parameterized in response to the requirements of, the first logic block. The bus interface blocks are connected to the first logic block in such a way that the first logic block is extended into a peripheral that can communicate with the bus.